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annotate defs/dgndefs @ 1971:136a4e706aa6

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Fixed step rate issues on recalibrate on original Dragon 5.25" drives
author afra
date Sun, 08 Jan 2006 21:39:17 +0000
parents 1e312b144f4d
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1804
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1 IFNE DGNDEFS-1
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2
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3 DGNDEFS set 1
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4
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5 ********************************************************************
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6 * DgnDefs - Dragon I/O Definitions
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7 *
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8 * $Id$
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9 *
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10 * Edt/Rev YYYY/MM/DD Modified by
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11 * Comment
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12 * ------------------------------------------------------------------
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13 * 2004/11/16 P.Harvey-Smith.
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14 * Fixed the stupid error I made in the defines below that made all the
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15 * non DPxxxxx defines equal to FF00 !!!
1806
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16 *
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17 * 2005/04/14 P.Harvey-Smith
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18 * Added non DP defines for ACIA on Dragon 64/Alpha
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19 *
1819
82bf619d5cc1 Fixed errors in defines in WD2797 registers
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20 * 2005/04/21 P.Harvey-Smith
82bf619d5cc1 Fixed errors in defines in WD2797 registers
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21 * Fixed errors in defines for WD2797 non-DP registers.
82bf619d5cc1 Fixed errors in defines in WD2797 registers
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22 *
82bf619d5cc1 Fixed errors in defines in WD2797 registers
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23
1804
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24 nam DgnDefs
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25 ttl Dragon I/O Definitions
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26
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27 ********************
1933
1e312b144f4d Major changes:
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28 * VTIO Static Memory
1728
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29 *
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30 * Definitions for ports on Dragon 32/64/Alpha.
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31 *
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32 *
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33 IO equ $ff00 IO page on Dragon
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34
78ce0a5ffc8e Incorporated changes and additions made by Phill Harvey-Smith for the
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35 *
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36 * Most of these symbols will be defined twice, as some
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37 * of the Dragon code, sets DP=$FF, and uses direct page
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38 * addressing to access the io ports, whilst some of it
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39 * uses absolute addressing.
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40 * The versions starting DP must be used with DP=$FF.
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41 *
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42
1804
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43 * PIA 0 and 1 standard on all Dragons.
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44 DPPIA0DA EQU $00 Side A Data/DDR
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45 DPPIA0CRA EQU $01 Side A Control.
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46 DPPIA0DB EQU $02 Side B Data/DDR
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47 DPPIA0CRB EQU $03 Side B Control.
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48
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49 PIA0DA EQU DPPIA0DA+IO Side A Data/DDR
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50 PIA0CRA EQU DPPIA0CRA+IO Side A Control.
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51 PIA0DB EQU DPPIA0DB+IO Side A Data/DDR
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52 PIA0CRB EQU DPPIA0CRB+IO Side A Control.
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53
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54 DPPIA1DA EQU $20 Side A Data/DDR
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55 DPPIA1CRA EQU $21 Side A Control.
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56 DPPIA1DB EQU $22 Side B Data/DDR
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57 DPPIA1CRB EQU $23 Side B Control.
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58
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59 PIA1DA EQU DPPIA1DA+IO Side A Data/DDR
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60 PIA1CRA EQU DPPIA1CRA+IO Side A Control.
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61 PIA1DB EQU DPPIA1DB+IO Side A Data/DDR
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62 PIA1CRB EQU DPPIA1CRB+IO Side A Control.
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63
1804
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64 * Dragon Alpha has a third PIA at $FF24.
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65 DPPIA2DA EQU $24 Side A Data/DDR
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66 DPPIA2CRA EQU $25 Side A Control.
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67 DPPIA2DB EQU $26 Side B Data/DDR
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68 DPPIA2CRB EQU $27 Side B Control.
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69
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70 PIA2DA EQU DPPIA2DA+IO Side A Data/DDR
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71 PIA2CRA EQU DPPIA2CRA+IO Side A Control.
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72 PIA2DB EQU DPPIA2DB+IO Side A Data/DDR
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73 PIA2CRB EQU DPPIA2CRB+IO Side A Control.
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74
1804
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75 * WD2797 Floppy disk controler, used in Alpha Note registers in reverse order !
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76 DPCmdRegA EQU $2F command/status
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77 DPTrkRegA EQU $2E Track register
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78 DPSecRegA EQU $2D Sector register
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79 DPDataRegA EQU $2C Data register
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80
1819
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81 CmdRegA EQU DPCMDREGA+IO command/status
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82 TrkRegA EQU DPTRKREGA+IO Track register
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83 SecRegA EQU DPSECREGA+IO Sector register
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84 DataRegA EQU DPDATAREGA+IO Data register
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85
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86 * Constants for Alpha AY-8912 sound chip, which is used to control
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87 * Drive select and motor on the Alpha
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88 AYIOREG EQU $0E AY-8912, IO Register number.
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89 AYIdle EQU $00 Make AY Idle.
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90 AYWriteReg EQU $01 Write AY Register
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91 AYReadReg EQU $02 Read AY Register
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92 AYREGLatch EQU $03 Latch register into AY
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93
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94 DSMask EQU $03 Drive select mask.
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95 MotorMask EQU $04 Motor enable mask
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96 DDENMask EQU $08 DDEN Mask
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97 ENPMask EQU $10 Enable Precomp mask
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98 NMIMask EQU $20 NMI enable Mask
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99
1804
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100 * Dragon 64/Alpha Serial port.
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101 DPAciaData EQU $04 ACIA Rx/Tx Register
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102 DPAciaStat EQU $05 ACIA status register
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103 DPAciaCmd EQU $06 ACIA command register
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104 DPAciaCtrl EQU $07 ACIA control register
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105
1806
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106 AciaData EQU DPAciaData+IO ACIA Rx/Tx Register
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107 AciaStat EQU DPAciaStat+IO ACIA status register
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108 AciaCmd EQU DPAciaCmd+IO ACIA command register
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109 AciaCtrl EQU DPAciaCtrl+IO ACIA control register
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110
1804
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111 * DragonDos Cartrage IO for WD2797
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112 * WD2797 Floppy disk controler, used in DragonDos.
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113 DPCmdRegD EQU $40 command/status
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114 DPTrkRegD EQU $41 Track register
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115 DPSecRegD EQU $42 Sector register
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116 DPDataRegD EQU $43 Data register
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117
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118 CmdRegD EQU DPCMDREGD+IO command/status
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119 TrkRegD EQU DPTRKREGD+IO Track register
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120 SecRegD EQU DPSECREGD+IO Sector register
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121 DataRegD EQU DPDATAREGD+IO Data register
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122
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123 DPDSKCTL EQU $48 Disk DS/motor control reg
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124 DSKCTL EQU DPDSKCTL+IO
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125
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126 * Disk IO bitmasks (DragonDos).
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127 NMIEnD EQU %00100000
1806
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128 WPCEnD EQU %00010000
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129 SDensEnD EQU %00001000
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130 MotorOnD EQU %00000100
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131 Drive0D EQU %00000000
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132 Drive1D EQU %00000001
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133 Drive2D EQU %00000010
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134 Drive3D EQU %00000011
1898
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135 DDosDriveMask EQU %00000011 Mask out all non drive select bits
c9f639d11d63 Added some minor defs for ddisk
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136 DDosCtrlMask EQU %11111100 Mask in all non drive select bits
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137
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138
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139 * Disk IO bitmasks (Dragon Alpha).
1898
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140 PIANMIEnA EQU %00001000 PIA2, CA2, used to enable/disable NMI
c9f639d11d63 Added some minor defs for ddisk
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141 PIANMIDisA EQU %11110111 Bitmask to force CA2 off, and disable NMI
c9f639d11d63 Added some minor defs for ddisk
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142
c9f639d11d63 Added some minor defs for ddisk
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143 NMIEnA EQU %10000000 Flag to enable disable NMI, passed to AlphaDskCtl
1806
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144 WPCEnA EQU %01000000 According to circuit trace by R.Harding.
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145 SDensEnA EQU %00100000 DDen, from circuit trace on R.Harding's machine.
1806
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146 MotorOnA EQU %00010000
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147 Drive0A EQU %00000001
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148 Drive1A EQU %00000010
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149 Drive2A EQU %00000100
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150 Drive3A EQU %00001000
1898
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151 AlphaDrvMask EQU %00001111 Mask out all non drive select bits
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152 AlphaCtrlMask EQU %11110000 Mask in all non drive select bits
1733
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153
1831
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154 Mask58 EQU %01111111 And mask to make sure 5.25" clock selected by WD2797
6fe4ae830c4d Fix for known alpha disk control bits.
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155
1843
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156 NMICA2En EQU $3C Value for PIA CRA to enable NMI
ed0f95f8caf4 Added defs for Alpha NMI disable
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157 NMICA2Dis EQU $34 Value for PIA CRA to disable NMI
ed0f95f8caf4 Added defs for Alpha NMI disable
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158
1733
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159 * Disk Commands
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160 FrcInt EQU %11010000
e6e8a44ab20a Updated by Phill
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161 ReadCmnd EQU %10001000
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162 RestCmnd EQU %00000000
e6e8a44ab20a Updated by Phill
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163 SeekCmnd EQU %00010000
e6e8a44ab20a Updated by Phill
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164 StpICmnd EQU %01000000
e6e8a44ab20a Updated by Phill
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165 WritCmnd EQU %10101000
e6e8a44ab20a Updated by Phill
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166 WtTkCmnd EQU %11110000
e6e8a44ab20a Updated by Phill
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167 Sid2Sel EQU %00000010
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168
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169 * Disk Status Bits
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170 BusyMask EQU %00000001
e6e8a44ab20a Updated by Phill
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171 LostMask EQU %00000100
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172 ErrMask EQU %11111000
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diff changeset
173 CRCMask EQU %00001000
e6e8a44ab20a Updated by Phill
boisy
parents: 1728
diff changeset
174 RNFMask EQU %00010000
e6e8a44ab20a Updated by Phill
boisy
parents: 1728
diff changeset
175 RTypMask EQU %00100000
e6e8a44ab20a Updated by Phill
boisy
parents: 1728
diff changeset
176 WPMask EQU %01000000
e6e8a44ab20a Updated by Phill
boisy
parents: 1728
diff changeset
177 NotRMask EQU %10000000
e6e8a44ab20a Updated by Phill
boisy
parents: 1728
diff changeset
178
e6e8a44ab20a Updated by Phill
boisy
parents: 1728
diff changeset
179 DensMask EQU %00000001
e6e8a44ab20a Updated by Phill
boisy
parents: 1728
diff changeset
180 T80Mask EQU %00000010
e6e8a44ab20a Updated by Phill
boisy
parents: 1728
diff changeset
181
1804
6e5fa42c2fb1 Cleaned up defs files
boisy
parents: 1733
diff changeset
182 ENDC