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annotate lib/CodeGen/VirtRegMap.cpp @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents 7d135dc70f03
children 803732b1fca8
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1 //===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file implements the VirtRegMap class.
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11 //
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12 // It also contains implementations of the Spiller interface, which, given a
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13 // virtual register map and a machine function, eliminates all virtual
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14 // references by replacing them with physical register references - adding spill
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15 // code as necessary.
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16 //
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17 //===----------------------------------------------------------------------===//
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18
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19 #include "llvm/CodeGen/VirtRegMap.h"
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20 #include "LiveDebugVariables.h"
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21 #include "llvm/ADT/STLExtras.h"
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22 #include "llvm/ADT/Statistic.h"
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23 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
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24 #include "llvm/CodeGen/LiveStackAnalysis.h"
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25 #include "llvm/CodeGen/MachineFrameInfo.h"
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26 #include "llvm/CodeGen/MachineFunction.h"
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27 #include "llvm/CodeGen/MachineInstrBuilder.h"
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28 #include "llvm/CodeGen/MachineRegisterInfo.h"
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29 #include "llvm/CodeGen/Passes.h"
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30 #include "llvm/IR/Function.h"
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31 #include "llvm/Support/Compiler.h"
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32 #include "llvm/Support/Debug.h"
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33 #include "llvm/Support/raw_ostream.h"
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34 #include "llvm/Target/TargetInstrInfo.h"
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35 #include "llvm/Target/TargetMachine.h"
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36 #include "llvm/Target/TargetRegisterInfo.h"
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37 #include "llvm/Target/TargetSubtargetInfo.h"
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38 #include <algorithm>
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39 using namespace llvm;
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40
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41 #define DEBUG_TYPE "regalloc"
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42
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43 STATISTIC(NumSpillSlots, "Number of spill slots allocated");
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44 STATISTIC(NumIdCopies, "Number of identity moves eliminated after rewriting");
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45
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46 //===----------------------------------------------------------------------===//
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47 // VirtRegMap implementation
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48 //===----------------------------------------------------------------------===//
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49
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50 char VirtRegMap::ID = 0;
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51
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52 INITIALIZE_PASS(VirtRegMap, "virtregmap", "Virtual Register Map", false, false)
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53
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54 bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
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55 MRI = &mf.getRegInfo();
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56 TII = mf.getSubtarget().getInstrInfo();
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57 TRI = mf.getSubtarget().getRegisterInfo();
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58 MF = &mf;
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59
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60 Virt2PhysMap.clear();
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61 Virt2StackSlotMap.clear();
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62 Virt2SplitMap.clear();
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63
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64 grow();
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65 return false;
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66 }
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67
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68 void VirtRegMap::grow() {
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69 unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
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70 Virt2PhysMap.resize(NumRegs);
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71 Virt2StackSlotMap.resize(NumRegs);
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72 Virt2SplitMap.resize(NumRegs);
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73 }
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74
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75 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
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76 int SS = MF->getFrameInfo().CreateSpillStackObject(RC->getSize(),
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77 RC->getAlignment());
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78 ++NumSpillSlots;
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79 return SS;
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80 }
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81
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82 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) {
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83 unsigned Hint = MRI->getSimpleHint(VirtReg);
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84 if (!Hint)
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85 return false;
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86 if (TargetRegisterInfo::isVirtualRegister(Hint))
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87 Hint = getPhys(Hint);
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88 return getPhys(VirtReg) == Hint;
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89 }
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90
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91 bool VirtRegMap::hasKnownPreference(unsigned VirtReg) {
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92 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg);
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93 if (TargetRegisterInfo::isPhysicalRegister(Hint.second))
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94 return true;
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95 if (TargetRegisterInfo::isVirtualRegister(Hint.second))
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96 return hasPhys(Hint.second);
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97 return false;
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98 }
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99
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100 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
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101 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
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102 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
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103 "attempt to assign stack slot to already spilled register");
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104 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
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105 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
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106 }
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107
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108 void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
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109 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
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110 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
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111 "attempt to assign stack slot to already spilled register");
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112 assert((SS >= 0 ||
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113 (SS >= MF->getFrameInfo().getObjectIndexBegin())) &&
0
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114 "illegal fixed frame index");
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115 Virt2StackSlotMap[virtReg] = SS;
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116 }
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117
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118 void VirtRegMap::print(raw_ostream &OS, const Module*) const {
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119 OS << "********** REGISTER MAP **********\n";
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120 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
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121 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
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122 if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
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123 OS << '[' << PrintReg(Reg, TRI) << " -> "
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124 << PrintReg(Virt2PhysMap[Reg], TRI) << "] "
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125 << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
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126 }
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127 }
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128
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129 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
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130 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
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131 if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
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132 OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
83
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133 << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
0
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134 }
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135 }
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136 OS << '\n';
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137 }
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138
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139 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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140 LLVM_DUMP_METHOD void VirtRegMap::dump() const {
0
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141 print(dbgs());
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142 }
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143 #endif
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144
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145 //===----------------------------------------------------------------------===//
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146 // VirtRegRewriter
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147 //===----------------------------------------------------------------------===//
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148 //
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149 // The VirtRegRewriter is the last of the register allocator passes.
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150 // It rewrites virtual registers to physical registers as specified in the
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151 // VirtRegMap analysis. It also updates live-in information on basic blocks
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152 // according to LiveIntervals.
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153 //
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154 namespace {
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155 class VirtRegRewriter : public MachineFunctionPass {
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156 MachineFunction *MF;
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157 const TargetMachine *TM;
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158 const TargetRegisterInfo *TRI;
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159 const TargetInstrInfo *TII;
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160 MachineRegisterInfo *MRI;
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161 SlotIndexes *Indexes;
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162 LiveIntervals *LIS;
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163 VirtRegMap *VRM;
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164
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165 void rewrite();
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166 void addMBBLiveIns();
95
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167 bool readsUndefSubreg(const MachineOperand &MO) const;
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168 void addLiveInsForSubRanges(const LiveInterval &LI, unsigned PhysReg) const;
120
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169 void handleIdentityCopy(MachineInstr &MI) const;
95
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170
0
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171 public:
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172 static char ID;
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173 VirtRegRewriter() : MachineFunctionPass(ID) {}
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174
77
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175 void getAnalysisUsage(AnalysisUsage &AU) const override;
0
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176
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diff changeset
177 bool runOnMachineFunction(MachineFunction&) override;
120
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178 MachineFunctionProperties getSetProperties() const override {
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179 return MachineFunctionProperties().set(
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180 MachineFunctionProperties::Property::NoVRegs);
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181 }
0
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182 };
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183 } // end anonymous namespace
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184
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185 char &llvm::VirtRegRewriterID = VirtRegRewriter::ID;
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186
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187 INITIALIZE_PASS_BEGIN(VirtRegRewriter, "virtregrewriter",
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188 "Virtual Register Rewriter", false, false)
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189 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
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190 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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191 INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
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192 INITIALIZE_PASS_DEPENDENCY(LiveStacks)
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193 INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
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194 INITIALIZE_PASS_END(VirtRegRewriter, "virtregrewriter",
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195 "Virtual Register Rewriter", false, false)
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196
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197 char VirtRegRewriter::ID = 0;
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198
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199 void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
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200 AU.setPreservesCFG();
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201 AU.addRequired<LiveIntervals>();
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202 AU.addRequired<SlotIndexes>();
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diff changeset
203 AU.addPreserved<SlotIndexes>();
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diff changeset
204 AU.addRequired<LiveDebugVariables>();
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diff changeset
205 AU.addRequired<LiveStacks>();
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206 AU.addPreserved<LiveStacks>();
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diff changeset
207 AU.addRequired<VirtRegMap>();
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diff changeset
208 MachineFunctionPass::getAnalysisUsage(AU);
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209 }
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210
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diff changeset
211 bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
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212 MF = &fn;
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diff changeset
213 TM = &MF->getTarget();
83
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diff changeset
214 TRI = MF->getSubtarget().getRegisterInfo();
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diff changeset
215 TII = MF->getSubtarget().getInstrInfo();
0
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diff changeset
216 MRI = &MF->getRegInfo();
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diff changeset
217 Indexes = &getAnalysis<SlotIndexes>();
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218 LIS = &getAnalysis<LiveIntervals>();
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diff changeset
219 VRM = &getAnalysis<VirtRegMap>();
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diff changeset
220 DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n"
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diff changeset
221 << "********** Function: "
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diff changeset
222 << MF->getName() << '\n');
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diff changeset
223 DEBUG(VRM->dump());
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diff changeset
224
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diff changeset
225 // Add kill flags while we still have virtual registers.
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diff changeset
226 LIS->addKillFlags(VRM);
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diff changeset
227
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228 // Live-in lists on basic blocks are required for physregs.
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diff changeset
229 addMBBLiveIns();
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diff changeset
230
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231 // Rewrite virtual registers.
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diff changeset
232 rewrite();
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diff changeset
233
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diff changeset
234 // Write out new DBG_VALUE instructions.
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diff changeset
235 getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
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diff changeset
236
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237 // All machine operands and other references to virtual registers have been
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diff changeset
238 // replaced. Remove the virtual registers and release all the transient data.
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diff changeset
239 VRM->clearAllVirt();
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diff changeset
240 MRI->clearVirtRegs();
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diff changeset
241 return true;
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diff changeset
242 }
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243
95
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diff changeset
244 void VirtRegRewriter::addLiveInsForSubRanges(const LiveInterval &LI,
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diff changeset
245 unsigned PhysReg) const {
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246 assert(!LI.empty());
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247 assert(LI.hasSubRanges());
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diff changeset
248
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diff changeset
249 typedef std::pair<const LiveInterval::SubRange *,
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parents: 83
diff changeset
250 LiveInterval::const_iterator> SubRangeIteratorPair;
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diff changeset
251 SmallVector<SubRangeIteratorPair, 4> SubRanges;
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diff changeset
252 SlotIndex First;
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diff changeset
253 SlotIndex Last;
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diff changeset
254 for (const LiveInterval::SubRange &SR : LI.subranges()) {
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diff changeset
255 SubRanges.push_back(std::make_pair(&SR, SR.begin()));
afa8332a0e37 LLVM 3.8
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parents: 83
diff changeset
256 if (!First.isValid() || SR.segments.front().start < First)
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parents: 83
diff changeset
257 First = SR.segments.front().start;
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diff changeset
258 if (!Last.isValid() || SR.segments.back().end > Last)
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diff changeset
259 Last = SR.segments.back().end;
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diff changeset
260 }
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diff changeset
261
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diff changeset
262 // Check all mbb start positions between First and Last while
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
263 // simulatenously advancing an iterator for each subrange.
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
264 for (SlotIndexes::MBBIndexIterator MBBI = Indexes->findMBBIndex(First);
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
265 MBBI != Indexes->MBBIndexEnd() && MBBI->first <= Last; ++MBBI) {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
266 SlotIndex MBBBegin = MBBI->first;
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
267 // Advance all subrange iterators so that their end position is just
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
268 // behind MBBBegin (or the iterator is at the end).
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
269 LaneBitmask LaneMask = 0;
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
270 for (auto &RangeIterPair : SubRanges) {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
271 const LiveInterval::SubRange *SR = RangeIterPair.first;
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
272 LiveInterval::const_iterator &SRI = RangeIterPair.second;
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
273 while (SRI != SR->end() && SRI->end <= MBBBegin)
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
274 ++SRI;
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
275 if (SRI == SR->end())
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
276 continue;
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
277 if (SRI->start <= MBBBegin)
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
278 LaneMask |= SR->LaneMask;
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
279 }
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
280 if (LaneMask == 0)
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
281 continue;
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
282 MachineBasicBlock *MBB = MBBI->second;
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
283 MBB->addLiveIn(PhysReg, LaneMask);
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
284 }
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
285 }
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
286
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
287 // Compute MBB live-in lists from virtual register live ranges and their
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
288 // assignments.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
289 void VirtRegRewriter::addMBBLiveIns() {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
290 for (unsigned Idx = 0, IdxE = MRI->getNumVirtRegs(); Idx != IdxE; ++Idx) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
291 unsigned VirtReg = TargetRegisterInfo::index2VirtReg(Idx);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
292 if (MRI->reg_nodbg_empty(VirtReg))
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
293 continue;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
294 LiveInterval &LI = LIS->getInterval(VirtReg);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
295 if (LI.empty() || LIS->intervalIsInOneMBB(LI))
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
296 continue;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
297 // This is a virtual register that is live across basic blocks. Its
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
298 // assigned PhysReg must be marked as live-in to those blocks.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
299 unsigned PhysReg = VRM->getPhys(VirtReg);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
300 assert(PhysReg != VirtRegMap::NO_PHYS_REG && "Unmapped virtual register.");
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
301
83
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
302 if (LI.hasSubRanges()) {
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
303 addLiveInsForSubRanges(LI, PhysReg);
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
304 } else {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
305 // Go over MBB begin positions and see if we have segments covering them.
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
306 // The following works because segments and the MBBIndex list are both
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
307 // sorted by slot indexes.
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
308 SlotIndexes::MBBIndexIterator I = Indexes->MBBIndexBegin();
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
309 for (const auto &Seg : LI) {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
310 I = Indexes->advanceMBBIndex(I, Seg.start);
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
311 for (; I != Indexes->MBBIndexEnd() && I->first < Seg.end; ++I) {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
312 MachineBasicBlock *MBB = I->second;
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
313 MBB->addLiveIn(PhysReg);
83
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
314 }
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
315 }
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
316 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
317 }
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
318
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
319 // Sort and unique MBB LiveIns as we've not checked if SubReg/PhysReg were in
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
320 // each MBB's LiveIns set before calling addLiveIn on them.
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
321 for (MachineBasicBlock &MBB : *MF)
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
322 MBB.sortUniqueLiveIns();
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
323 }
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
324
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
325 /// Returns true if the given machine operand \p MO only reads undefined lanes.
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
326 /// The function only works for use operands with a subregister set.
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
327 bool VirtRegRewriter::readsUndefSubreg(const MachineOperand &MO) const {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
328 // Shortcut if the operand is already marked undef.
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
329 if (MO.isUndef())
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
330 return true;
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
331
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
332 unsigned Reg = MO.getReg();
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
333 const LiveInterval &LI = LIS->getInterval(Reg);
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
334 const MachineInstr &MI = *MO.getParent();
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
335 SlotIndex BaseIndex = LIS->getInstructionIndex(MI);
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
336 // This code is only meant to handle reading undefined subregisters which
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
337 // we couldn't properly detect before.
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
338 assert(LI.liveAt(BaseIndex) &&
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
339 "Reads of completely dead register should be marked undef already");
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
340 unsigned SubRegIdx = MO.getSubReg();
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
341 assert(SubRegIdx != 0 && LI.hasSubRanges());
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
342 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx);
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
343 // See if any of the relevant subregister liveranges is defined at this point.
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
344 for (const LiveInterval::SubRange &SR : LI.subranges()) {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
345 if ((SR.LaneMask & UseMask) != 0 && SR.liveAt(BaseIndex))
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
346 return false;
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
347 }
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
348 return true;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
349 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
350
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
351 void VirtRegRewriter::handleIdentityCopy(MachineInstr &MI) const {
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
352 if (!MI.isIdentityCopy())
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
353 return;
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
354 DEBUG(dbgs() << "Identity copy: " << MI);
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
355 ++NumIdCopies;
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
356
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
357 // Copies like:
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
358 // %R0 = COPY %R0<undef>
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
359 // %AL = COPY %AL, %EAX<imp-def>
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
360 // give us additional liveness information: The target (super-)register
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
361 // must not be valid before this point. Replace the COPY with a KILL
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
362 // instruction to maintain this information.
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
363 if (MI.getOperand(0).isUndef() || MI.getNumOperands() > 2) {
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
364 MI.setDesc(TII->get(TargetOpcode::KILL));
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
365 DEBUG(dbgs() << " replace by: " << MI);
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
366 return;
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
367 }
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
368
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
369 if (Indexes)
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
370 Indexes->removeMachineInstrFromMaps(MI);
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
371 MI.eraseFromParent();
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
372 DEBUG(dbgs() << " deleted.\n");
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
373 }
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
374
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
375 void VirtRegRewriter::rewrite() {
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
376 bool NoSubRegLiveness = !MRI->subRegLivenessEnabled();
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
377 SmallVector<unsigned, 8> SuperDeads;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
378 SmallVector<unsigned, 8> SuperDefs;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
379 SmallVector<unsigned, 8> SuperKills;
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
380
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
381 for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
382 MBBI != MBBE; ++MBBI) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
383 DEBUG(MBBI->print(dbgs(), Indexes));
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
384 for (MachineBasicBlock::instr_iterator
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
385 MII = MBBI->instr_begin(), MIE = MBBI->instr_end(); MII != MIE;) {
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
386 MachineInstr *MI = &*MII;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
387 ++MII;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
388
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
389 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
390 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
391 MachineOperand &MO = *MOI;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
392
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
393 // Make sure MRI knows about registers clobbered by regmasks.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
394 if (MO.isRegMask())
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
395 MRI->addPhysRegsUsedFromRegMask(MO.getRegMask());
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
396
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
397 if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
398 continue;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
399 unsigned VirtReg = MO.getReg();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
400 unsigned PhysReg = VRM->getPhys(VirtReg);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
401 assert(PhysReg != VirtRegMap::NO_PHYS_REG &&
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
402 "Instruction uses unmapped VirtReg");
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
403 assert(!MRI->isReserved(PhysReg) && "Reserved register assignment");
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
404
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
405 // Preserve semantics of sub-register operands.
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
406 unsigned SubReg = MO.getSubReg();
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
407 if (SubReg != 0) {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
408 if (NoSubRegLiveness) {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
409 // A virtual register kill refers to the whole register, so we may
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
410 // have to add <imp-use,kill> operands for the super-register. A
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
411 // partial redef always kills and redefines the super-register.
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
412 if (MO.readsReg() && (MO.isDef() || MO.isKill()))
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
413 SuperKills.push_back(PhysReg);
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
414
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
415 if (MO.isDef()) {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
416 // Also add implicit defs for the super-register.
83
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
417 if (MO.isDead())
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
418 SuperDeads.push_back(PhysReg);
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
419 else
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
420 SuperDefs.push_back(PhysReg);
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
421 }
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
422 } else {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
423 if (MO.isUse()) {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
424 if (readsUndefSubreg(MO))
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
425 // We need to add an <undef> flag if the subregister is
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
426 // completely undefined (and we are not adding super-register
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
427 // defs).
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
428 MO.setIsUndef(true);
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
429 } else if (!MO.isDead()) {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
430 assert(MO.isDef());
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
431 }
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
432 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
433
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
434 // The <def,undef> flag only makes sense for sub-register defs, and
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
435 // we are substituting a full physreg. An <imp-use,kill> operand
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
436 // from the SuperKills list will represent the partial read of the
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
437 // super-register.
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
438 if (MO.isDef())
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
439 MO.setIsUndef(false);
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
440
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
441 // PhysReg operands cannot have subregister indexes.
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
442 PhysReg = TRI->getSubReg(PhysReg, SubReg);
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
443 assert(PhysReg && "Invalid SubReg for physical register");
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
444 MO.setSubReg(0);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
445 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
446 // Rewrite. Note we could have used MachineOperand::substPhysReg(), but
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
447 // we need the inlining here.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
448 MO.setReg(PhysReg);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
449 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
450
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
451 // Add any missing super-register kills after rewriting the whole
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
452 // instruction.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
453 while (!SuperKills.empty())
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
454 MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
455
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
456 while (!SuperDeads.empty())
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
457 MI->addRegisterDead(SuperDeads.pop_back_val(), TRI, true);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
458
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
459 while (!SuperDefs.empty())
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
460 MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
461
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
462 DEBUG(dbgs() << "> " << *MI);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
463
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
464 // We can remove identity copies right now.
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
465 handleIdentityCopy(*MI);
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
466 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
467 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
468 }