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annotate lib/Target/PowerPC/PPCInstrInfo.h @ 100:7d135dc70f03

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children 1172e4bd9c6f
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1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
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15 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
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16
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17 #include "PPC.h"
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18 #include "PPCRegisterInfo.h"
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19 #include "llvm/Target/TargetInstrInfo.h"
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20
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21 #define GET_INSTRINFO_HEADER
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22 #include "PPCGenInstrInfo.inc"
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23
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24 namespace llvm {
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25
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26 /// PPCII - This namespace holds all of the PowerPC target-specific
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27 /// per-instruction flags. These must match the corresponding definitions in
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28 /// PPC.td and PPCInstrFormats.td.
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29 namespace PPCII {
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30 enum {
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31 // PPC970 Instruction Flags. These flags describe the characteristics of the
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32 // PowerPC 970 (aka G5) dispatch groups and how they are formed out of
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33 // raw machine instructions.
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34
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35 /// PPC970_First - This instruction starts a new dispatch group, so it will
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36 /// always be the first one in the group.
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37 PPC970_First = 0x1,
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38
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39 /// PPC970_Single - This instruction starts a new dispatch group and
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40 /// terminates it, so it will be the sole instruction in the group.
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41 PPC970_Single = 0x2,
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42
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43 /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
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44 /// two dispatch pipes to be available to issue.
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45 PPC970_Cracked = 0x4,
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46
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47 /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
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48 /// an instruction is issued to.
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49 PPC970_Shift = 3,
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50 PPC970_Mask = 0x07 << PPC970_Shift
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51 };
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52 enum PPC970_Unit {
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53 /// These are the various PPC970 execution unit pipelines. Each instruction
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54 /// is one of these.
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55 PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction
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56 PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit
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57 PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit
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58 PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit
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59 PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit
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60 PPC970_VALU = 5 << PPC970_Shift, // Vector ALU
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61 PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit
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62 PPC970_BRU = 7 << PPC970_Shift // Branch Unit
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63 };
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64 } // end namespace PPCII
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65
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66 class PPCSubtarget;
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67 class PPCInstrInfo : public PPCGenInstrInfo {
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68 PPCSubtarget &Subtarget;
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69 const PPCRegisterInfo RI;
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70
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71 bool StoreRegToStackSlot(MachineFunction &MF,
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72 unsigned SrcReg, bool isKill, int FrameIdx,
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73 const TargetRegisterClass *RC,
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74 SmallVectorImpl<MachineInstr*> &NewMIs,
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75 bool &NonRI, bool &SpillsVRS) const;
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76 bool LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
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77 unsigned DestReg, int FrameIdx,
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78 const TargetRegisterClass *RC,
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79 SmallVectorImpl<MachineInstr*> &NewMIs,
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80 bool &NonRI, bool &SpillsVRS) const;
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81 virtual void anchor();
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82
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83 protected:
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84 /// Commutes the operands in the given instruction.
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85 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
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86 ///
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87 /// Do not call this method for a non-commutable instruction or for
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88 /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
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89 /// Even though the instruction is commutable, the method may still
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90 /// fail to commute the operands, null pointer is returned in such cases.
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91 ///
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92 /// For example, we can commute rlwimi instructions, but only if the
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93 /// rotate amt is zero. We also have to munge the immediates a bit.
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94 MachineInstr *commuteInstructionImpl(MachineInstr *MI,
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95 bool NewMI,
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96 unsigned OpIdx1,
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97 unsigned OpIdx2) const override;
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98
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99 public:
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100 explicit PPCInstrInfo(PPCSubtarget &STI);
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101
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102 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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103 /// such, whenever a client has an instance of instruction info, it should
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104 /// always be able to get register info as well (through this method).
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105 ///
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106 const PPCRegisterInfo &getRegisterInfo() const { return RI; }
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107
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108 ScheduleHazardRecognizer *
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109 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
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110 const ScheduleDAG *DAG) const override;
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111 ScheduleHazardRecognizer *
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112 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
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113 const ScheduleDAG *DAG) const override;
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114
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115 unsigned getInstrLatency(const InstrItineraryData *ItinData,
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116 const MachineInstr *MI,
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117 unsigned *PredCost = nullptr) const override;
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118
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119 int getOperandLatency(const InstrItineraryData *ItinData,
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120 const MachineInstr *DefMI, unsigned DefIdx,
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121 const MachineInstr *UseMI,
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122 unsigned UseIdx) const override;
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123 int getOperandLatency(const InstrItineraryData *ItinData,
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124 SDNode *DefNode, unsigned DefIdx,
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125 SDNode *UseNode, unsigned UseIdx) const override {
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126 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
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127 UseNode, UseIdx);
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128 }
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129
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130 bool hasLowDefLatency(const TargetSchedModel &SchedModel,
83
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131 const MachineInstr *DefMI,
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132 unsigned DefIdx) const override {
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133 // Machine LICM should hoist all instructions in low-register-pressure
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134 // situations; none are sufficiently free to justify leaving in a loop
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135 // body.
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136 return false;
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137 }
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138
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139 bool useMachineCombiner() const override {
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140 return true;
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141 }
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142
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143 /// Return true when there is potentially a faster code sequence
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144 /// for an instruction chain ending in <Root>. All potential patterns are
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145 /// output in the <Pattern> array.
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146 bool getMachineCombinerPatterns(
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147 MachineInstr &Root,
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148 SmallVectorImpl<MachineCombinerPattern> &P) const override;
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149
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150 bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
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151
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152 bool isCoalescableExtInstr(const MachineInstr &MI,
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153 unsigned &SrcReg, unsigned &DstReg,
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154 unsigned &SubIdx) const override;
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155 unsigned isLoadFromStackSlot(const MachineInstr *MI,
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156 int &FrameIndex) const override;
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157 unsigned isStoreToStackSlot(const MachineInstr *MI,
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158 int &FrameIndex) const override;
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159
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160 bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
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161 unsigned &SrcOpIdx2) const override;
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162
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163 void insertNoop(MachineBasicBlock &MBB,
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164 MachineBasicBlock::iterator MI) const override;
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165
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166
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167 // Branch analysis.
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168 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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169 MachineBasicBlock *&FBB,
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170 SmallVectorImpl<MachineOperand> &Cond,
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171 bool AllowModify) const override;
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172 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
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173 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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174 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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175 DebugLoc DL) const override;
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176
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177 // Select analysis.
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178 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
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179 unsigned, unsigned, int &, int &, int &) const override;
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180 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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181 DebugLoc DL, unsigned DstReg, ArrayRef<MachineOperand> Cond,
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182 unsigned TrueReg, unsigned FalseReg) const override;
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183
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184 void copyPhysReg(MachineBasicBlock &MBB,
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185 MachineBasicBlock::iterator I, DebugLoc DL,
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186 unsigned DestReg, unsigned SrcReg,
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187 bool KillSrc) const override;
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188
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189 void storeRegToStackSlot(MachineBasicBlock &MBB,
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190 MachineBasicBlock::iterator MBBI,
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191 unsigned SrcReg, bool isKill, int FrameIndex,
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192 const TargetRegisterClass *RC,
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193 const TargetRegisterInfo *TRI) const override;
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194
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195 void loadRegFromStackSlot(MachineBasicBlock &MBB,
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196 MachineBasicBlock::iterator MBBI,
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197 unsigned DestReg, int FrameIndex,
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198 const TargetRegisterClass *RC,
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199 const TargetRegisterInfo *TRI) const override;
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200
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201 bool
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202 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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203
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204 bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
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205 unsigned Reg, MachineRegisterInfo *MRI) const override;
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206
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207 // If conversion by predication (only supported by some branch instructions).
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208 // All of the profitability checks always return true; it is always
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209 // profitable to use the predicated branches.
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210 bool isProfitableToIfCvt(MachineBasicBlock &MBB,
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211 unsigned NumCycles, unsigned ExtraPredCycles,
95
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212 BranchProbability Probability) const override {
0
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213 return true;
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214 }
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215
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216 bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
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217 unsigned NumT, unsigned ExtraT,
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218 MachineBasicBlock &FMBB,
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219 unsigned NumF, unsigned ExtraF,
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220 BranchProbability Probability) const override;
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221
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222 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
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223 BranchProbability Probability) const override {
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224 return true;
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225 }
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226
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227 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
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228 MachineBasicBlock &FMBB) const override {
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229 return false;
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230 }
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231
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232 // Predication support.
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233 bool isPredicated(const MachineInstr *MI) const override;
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234
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235 bool isUnpredicatedTerminator(const MachineInstr *MI) const override;
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diff changeset
236
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237 bool PredicateInstruction(MachineInstr *MI,
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238 ArrayRef<MachineOperand> Pred) const override;
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239
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240 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
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241 ArrayRef<MachineOperand> Pred2) const override;
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242
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243 bool DefinesPredicate(MachineInstr *MI,
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diff changeset
244 std::vector<MachineOperand> &Pred) const override;
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245
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246 bool isPredicable(MachineInstr *MI) const override;
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247
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248 // Comparison optimization.
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249
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250
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251 bool analyzeCompare(const MachineInstr *MI,
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diff changeset
252 unsigned &SrcReg, unsigned &SrcReg2,
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253 int &Mask, int &Value) const override;
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254
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diff changeset
255 bool optimizeCompareInstr(MachineInstr *CmpInstr,
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diff changeset
256 unsigned SrcReg, unsigned SrcReg2,
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diff changeset
257 int Mask, int Value,
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diff changeset
258 const MachineRegisterInfo *MRI) const override;
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259
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260 /// GetInstSize - Return the number of bytes of code the specified
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261 /// instruction may be. This returns the maximum number of bytes.
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262 ///
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263 unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
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264
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265 void getNoopForMachoTarget(MCInst &NopInst) const override;
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266
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267 std::pair<unsigned, unsigned>
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268 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
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269
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270 ArrayRef<std::pair<unsigned, const char *>>
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271 getSerializableDirectMachineOperandTargetFlags() const override;
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272
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273 ArrayRef<std::pair<unsigned, const char *>>
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274 getSerializableBitmaskMachineOperandTargetFlags() const override;
0
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275 };
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276
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277 }
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278
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279 #endif