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1 //===- X86InstrVecCompiler.td - Vector Compiler Patterns ---*- tablegen -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file describes the various vector pseudo instructions used by the
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11 // compiler, as well as Pat patterns used during instruction selection.
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12 //
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13 //===----------------------------------------------------------------------===//
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14
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15 //===----------------------------------------------------------------------===//
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16 // No op bitconverts
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17 //===----------------------------------------------------------------------===//
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18
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19 // Bitcasts between 128-bit vector types. Return the original type since
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20 // no instruction is needed for the conversion
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21 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
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22 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
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23 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
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24 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
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25 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
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26 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
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27 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
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28 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
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29 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
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30 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
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31 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
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32 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
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33 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
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34 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
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35 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
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36 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
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37 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
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38 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
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39 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
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40 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
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41 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
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42 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
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43 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
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44 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
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45 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
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46 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
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47 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
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48 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
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49 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
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50 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
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51 def : Pat<(f128 (bitconvert (i128 FR128:$src))), (f128 FR128:$src)>;
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52 def : Pat<(i128 (bitconvert (f128 FR128:$src))), (i128 FR128:$src)>;
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53
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54 // Bitcasts between 256-bit vector types. Return the original type since
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55 // no instruction is needed for the conversion
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56 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
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57 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
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58 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
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59 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
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60 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
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61 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
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62 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
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63 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
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64 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
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65 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
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66 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
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67 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
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68 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
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69 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
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70 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
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71 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
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72 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
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73 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
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74 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
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75 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
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76 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
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77 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
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78 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
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79 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
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80 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
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81 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
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82 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
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83 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
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84 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
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85 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
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86
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87 // Bitcasts between 512-bit vector types. Return the original type since
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88 // no instruction is needed for the conversion.
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89 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
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90 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
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91 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
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92 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
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93 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
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94 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
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95 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
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96 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
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97 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
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98 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
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99 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
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100 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
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101 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
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102 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
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103 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
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104 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
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105 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
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106 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
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107 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
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108 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
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109 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
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110 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
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111 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
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112 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
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113 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
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114 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
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115 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
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116 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
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117 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
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118 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
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119 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
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120
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121
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122 //===----------------------------------------------------------------------===//
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123 // Non-instruction patterns
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124 //===----------------------------------------------------------------------===//
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125
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126 // A vector extract of the first f32/f64 position is a subregister copy
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127 def : Pat<(f32 (extractelt (v4f32 VR128:$src), (iPTR 0))),
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128 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
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129 def : Pat<(f64 (extractelt (v2f64 VR128:$src), (iPTR 0))),
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130 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
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131
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132 // Implicitly promote a 32-bit scalar to a vector.
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133 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
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134 (COPY_TO_REGCLASS FR32:$src, VR128)>;
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135 // Implicitly promote a 64-bit scalar to a vector.
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136 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
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137 (COPY_TO_REGCLASS FR64:$src, VR128)>;
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138
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139
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140 //===----------------------------------------------------------------------===//
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141 // Subvector tricks
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142 //===----------------------------------------------------------------------===//
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143
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144 // Patterns for insert_subvector/extract_subvector to/from index=0
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145 multiclass subvector_subreg_lowering<RegisterClass subRC, ValueType subVT,
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146 RegisterClass RC, ValueType VT,
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147 SubRegIndex subIdx> {
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148 def : Pat<(subVT (extract_subvector (VT RC:$src), (iPTR 0))),
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149 (subVT (EXTRACT_SUBREG RC:$src, subIdx))>;
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150
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151 let AddedComplexity = 25 in // to give priority over vinsertf128rm
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152 def : Pat<(VT (insert_subvector undef, subRC:$src, (iPTR 0))),
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153 (VT (INSERT_SUBREG (IMPLICIT_DEF), subRC:$src, subIdx))>;
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154 }
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155
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156 // A 128-bit subvector extract from the first 256-bit vector position is a
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157 // subregister copy that needs no instruction. Likewise, a 128-bit subvector
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158 // insert to the first 256-bit vector position is a subregister copy that needs
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159 // no instruction.
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160 defm : subvector_subreg_lowering<VR128, v4i32, VR256, v8i32, sub_xmm>;
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161 defm : subvector_subreg_lowering<VR128, v4f32, VR256, v8f32, sub_xmm>;
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162 defm : subvector_subreg_lowering<VR128, v2i64, VR256, v4i64, sub_xmm>;
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163 defm : subvector_subreg_lowering<VR128, v2f64, VR256, v4f64, sub_xmm>;
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164 defm : subvector_subreg_lowering<VR128, v8i16, VR256, v16i16, sub_xmm>;
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165 defm : subvector_subreg_lowering<VR128, v16i8, VR256, v32i8, sub_xmm>;
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166
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167 // A 128-bit subvector extract from the first 512-bit vector position is a
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168 // subregister copy that needs no instruction. Likewise, a 128-bit subvector
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169 // insert to the first 512-bit vector position is a subregister copy that needs
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170 // no instruction.
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171 defm : subvector_subreg_lowering<VR128, v4i32, VR512, v16i32, sub_xmm>;
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172 defm : subvector_subreg_lowering<VR128, v4f32, VR512, v16f32, sub_xmm>;
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173 defm : subvector_subreg_lowering<VR128, v2i64, VR512, v8i64, sub_xmm>;
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174 defm : subvector_subreg_lowering<VR128, v2f64, VR512, v8f64, sub_xmm>;
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175 defm : subvector_subreg_lowering<VR128, v8i16, VR512, v32i16, sub_xmm>;
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176 defm : subvector_subreg_lowering<VR128, v16i8, VR512, v64i8, sub_xmm>;
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177
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178 // A 128-bit subvector extract from the first 512-bit vector position is a
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179 // subregister copy that needs no instruction. Likewise, a 128-bit subvector
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180 // insert to the first 512-bit vector position is a subregister copy that needs
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181 // no instruction.
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182 defm : subvector_subreg_lowering<VR256, v8i32, VR512, v16i32, sub_ymm>;
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183 defm : subvector_subreg_lowering<VR256, v8f32, VR512, v16f32, sub_ymm>;
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184 defm : subvector_subreg_lowering<VR256, v4i64, VR512, v8i64, sub_ymm>;
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185 defm : subvector_subreg_lowering<VR256, v4f64, VR512, v8f64, sub_ymm>;
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186 defm : subvector_subreg_lowering<VR256, v16i16, VR512, v32i16, sub_ymm>;
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187 defm : subvector_subreg_lowering<VR256, v32i8, VR512, v64i8, sub_ymm>;
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188
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189
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190 multiclass subvector_store_lowering<string AlignedStr, string UnalignedStr,
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191 RegisterClass RC, ValueType DstTy,
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192 ValueType SrcTy, SubRegIndex SubIdx> {
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193 def : Pat<(alignedstore (DstTy (extract_subvector
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194 (SrcTy RC:$src), (iPTR 0))), addr:$dst),
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195 (!cast<Instruction>("VMOV"#AlignedStr#"mr") addr:$dst,
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196 (DstTy (EXTRACT_SUBREG RC:$src, SubIdx)))>;
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197
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198 def : Pat<(store (DstTy (extract_subvector
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199 (SrcTy RC:$src), (iPTR 0))), addr:$dst),
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200 (!cast<Instruction>("VMOV"#UnalignedStr#"mr") addr:$dst,
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201 (DstTy (EXTRACT_SUBREG RC:$src, SubIdx)))>;
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202 }
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203
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204 let Predicates = [HasAVX, NoVLX] in {
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205 defm : subvector_store_lowering<"APD", "UPD", VR256X, v2f64, v4f64, sub_xmm>;
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206 defm : subvector_store_lowering<"APS", "UPS", VR256X, v4f32, v8f32, sub_xmm>;
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207 defm : subvector_store_lowering<"DQA", "DQU", VR256X, v2i64, v4i64, sub_xmm>;
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208 defm : subvector_store_lowering<"DQA", "DQU", VR256X, v4i32, v8i32, sub_xmm>;
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209 defm : subvector_store_lowering<"DQA", "DQU", VR256X, v8i16, v16i16, sub_xmm>;
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210 defm : subvector_store_lowering<"DQA", "DQU", VR256X, v16i8, v32i8, sub_xmm>;
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211 }
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212
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213 let Predicates = [HasVLX] in {
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214 // Special patterns for storing subvector extracts of lower 128-bits
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215 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
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216 defm : subvector_store_lowering<"APDZ128", "UPDZ128", VR256X, v2f64, v4f64,
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217 sub_xmm>;
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218 defm : subvector_store_lowering<"APSZ128", "UPSZ128", VR256X, v4f32, v8f32,
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219 sub_xmm>;
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220 defm : subvector_store_lowering<"DQA32Z128", "DQU32Z128", VR256X, v2i64,
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221 v4i64, sub_xmm>;
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222 defm : subvector_store_lowering<"DQA32Z128", "DQU32Z128", VR256X, v4i32,
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223 v8i32, sub_xmm>;
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224 defm : subvector_store_lowering<"DQA32Z128", "DQU32Z128", VR256X, v8i16,
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225 v16i16, sub_xmm>;
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226 defm : subvector_store_lowering<"DQA32Z128", "DQU32Z128", VR256X, v16i8,
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227 v32i8, sub_xmm>;
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228
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229 // Special patterns for storing subvector extracts of lower 128-bits of 512.
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230 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
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231 defm : subvector_store_lowering<"APDZ128", "UPDZ128", VR512, v2f64, v8f64,
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232 sub_xmm>;
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233 defm : subvector_store_lowering<"APSZ128", "UPSZ128", VR512, v4f32, v16f32,
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234 sub_xmm>;
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235 defm : subvector_store_lowering<"DQA32Z128", "DQU32Z128", VR512, v2i64,
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236 v8i64, sub_xmm>;
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237 defm : subvector_store_lowering<"DQA32Z128", "DQU32Z128", VR512, v4i32,
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238 v16i32, sub_xmm>;
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239 defm : subvector_store_lowering<"DQA32Z128", "DQU32Z128", VR512, v8i16,
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240 v32i16, sub_xmm>;
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241 defm : subvector_store_lowering<"DQA32Z128", "DQU32Z128", VR512, v16i8,
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242 v64i8, sub_xmm>;
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243
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244 // Special patterns for storing subvector extracts of lower 256-bits of 512.
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245 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
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246 defm : subvector_store_lowering<"APDZ256", "UPDZ256", VR512, v4f64, v8f64,
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247 sub_ymm>;
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248 defm : subvector_store_lowering<"APSZ256", "UPSZ256", VR512, v8f32, v16f32,
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249 sub_ymm>;
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250 defm : subvector_store_lowering<"DQA32Z256", "DQU32Z256", VR512, v4i64,
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251 v8i64, sub_ymm>;
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252 defm : subvector_store_lowering<"DQA32Z256", "DQU32Z256", VR512, v8i32,
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253 v16i32, sub_ymm>;
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254 defm : subvector_store_lowering<"DQA32Z256", "DQU32Z256", VR512, v16i16,
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255 v32i16, sub_ymm>;
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256 defm : subvector_store_lowering<"DQA32Z256", "DQU32Z256", VR512, v32i8,
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257 v64i8, sub_ymm>;
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258 }
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259
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260 // If we're inserting into an all zeros vector, just use a plain move which
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261 // will zero the upper bits.
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262 // TODO: Is there a safe way to detect whether the producing instruction
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263 // already zeroed the upper bits?
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264 multiclass subvector_zero_lowering<string MoveStr, RegisterClass RC,
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265 ValueType DstTy, ValueType SrcTy,
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266 ValueType ZeroTy, PatFrag memop,
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267 SubRegIndex SubIdx> {
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268 def : Pat<(DstTy (insert_subvector (bitconvert (ZeroTy immAllZerosV)),
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269 (SrcTy RC:$src), (iPTR 0))),
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270 (SUBREG_TO_REG (i64 0),
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271 (!cast<Instruction>("VMOV"#MoveStr#"rr") RC:$src), SubIdx)>;
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272
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273 def : Pat<(DstTy (insert_subvector (bitconvert (ZeroTy immAllZerosV)),
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274 (SrcTy (bitconvert (memop addr:$src))),
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275 (iPTR 0))),
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276 (SUBREG_TO_REG (i64 0),
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277 (!cast<Instruction>("VMOV"#MoveStr#"rm") addr:$src), SubIdx)>;
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278 }
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279
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280 let Predicates = [HasAVX, NoVLX] in {
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281 defm : subvector_zero_lowering<"APD", VR128, v4f64, v2f64, v8i32, loadv2f64,
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282 sub_xmm>;
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283 defm : subvector_zero_lowering<"APS", VR128, v8f32, v4f32, v8i32, loadv4f32,
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284 sub_xmm>;
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285 defm : subvector_zero_lowering<"DQA", VR128, v4i64, v2i64, v8i32, loadv2i64,
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286 sub_xmm>;
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287 defm : subvector_zero_lowering<"DQA", VR128, v8i32, v4i32, v8i32, loadv2i64,
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288 sub_xmm>;
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289 defm : subvector_zero_lowering<"DQA", VR128, v16i16, v8i16, v8i32, loadv2i64,
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290 sub_xmm>;
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291 defm : subvector_zero_lowering<"DQA", VR128, v32i8, v16i8, v8i32, loadv2i64,
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292 sub_xmm>;
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293 }
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294
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295 let Predicates = [HasVLX] in {
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296 defm : subvector_zero_lowering<"APDZ128", VR128X, v4f64, v2f64, v8i32,
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297 loadv2f64, sub_xmm>;
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298 defm : subvector_zero_lowering<"APSZ128", VR128X, v8f32, v4f32, v8i32,
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299 loadv4f32, sub_xmm>;
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300 defm : subvector_zero_lowering<"DQA64Z128", VR128X, v4i64, v2i64, v8i32,
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301 loadv2i64, sub_xmm>;
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302 defm : subvector_zero_lowering<"DQA64Z128", VR128X, v8i32, v4i32, v8i32,
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303 loadv2i64, sub_xmm>;
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304 defm : subvector_zero_lowering<"DQA64Z128", VR128X, v16i16, v8i16, v8i32,
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305 loadv2i64, sub_xmm>;
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306 defm : subvector_zero_lowering<"DQA64Z128", VR128X, v32i8, v16i8, v8i32,
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307 loadv2i64, sub_xmm>;
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308
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309 defm : subvector_zero_lowering<"APDZ128", VR128X, v8f64, v2f64, v16i32,
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310 loadv2f64, sub_xmm>;
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311 defm : subvector_zero_lowering<"APSZ128", VR128X, v16f32, v4f32, v16i32,
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312 loadv4f32, sub_xmm>;
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313 defm : subvector_zero_lowering<"DQA64Z128", VR128X, v8i64, v2i64, v16i32,
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314 loadv2i64, sub_xmm>;
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315 defm : subvector_zero_lowering<"DQA64Z128", VR128X, v16i32, v4i32, v16i32,
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316 loadv2i64, sub_xmm>;
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317 defm : subvector_zero_lowering<"DQA64Z128", VR128X, v32i16, v8i16, v16i32,
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318 loadv2i64, sub_xmm>;
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319 defm : subvector_zero_lowering<"DQA64Z128", VR128X, v64i8, v16i8, v16i32,
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320 loadv2i64, sub_xmm>;
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321
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322 defm : subvector_zero_lowering<"APDZ256", VR256X, v8f64, v4f64, v16i32,
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323 loadv4f64, sub_ymm>;
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324 defm : subvector_zero_lowering<"APSZ256", VR256X, v16f32, v8f32, v16i32,
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325 loadv8f32, sub_ymm>;
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326 defm : subvector_zero_lowering<"DQA64Z256", VR256X, v8i64, v4i64, v16i32,
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327 loadv4i64, sub_ymm>;
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328 defm : subvector_zero_lowering<"DQA64Z256", VR256X, v16i32, v8i32, v16i32,
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329 loadv4i64, sub_ymm>;
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330 defm : subvector_zero_lowering<"DQA64Z256", VR256X, v32i16, v16i16, v16i32,
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331 loadv4i64, sub_ymm>;
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332 defm : subvector_zero_lowering<"DQA64Z256", VR256X, v64i8, v32i8, v16i32,
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333 loadv4i64, sub_ymm>;
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334 }
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335
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336 let Predicates = [HasAVX512, NoVLX] in {
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337 defm : subvector_zero_lowering<"APD", VR128, v8f64, v2f64, v16i32, loadv2f64,
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338 sub_xmm>;
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339 defm : subvector_zero_lowering<"APS", VR128, v16f32, v4f32, v16i32, loadv4f32,
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340 sub_xmm>;
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341 defm : subvector_zero_lowering<"DQA", VR128, v8i64, v2i64, v16i32, loadv2i64,
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342 sub_xmm>;
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343 defm : subvector_zero_lowering<"DQA", VR128, v16i32, v4i32, v16i32, loadv2i64,
|
|
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344 sub_xmm>;
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345 defm : subvector_zero_lowering<"DQA", VR128, v32i16, v8i16, v16i32, loadv2i64,
|
|
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346 sub_xmm>;
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347 defm : subvector_zero_lowering<"DQA", VR128, v64i8, v16i8, v16i32, loadv2i64,
|
|
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348 sub_xmm>;
|
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349
|
|
|
350 defm : subvector_zero_lowering<"APDY", VR256, v8f64, v4f64, v16i32,
|
|
|
351 loadv4f64, sub_ymm>;
|
|
|
352 defm : subvector_zero_lowering<"APSY", VR256, v16f32, v8f32, v16i32,
|
|
|
353 loadv8f32, sub_ymm>;
|
|
|
354 defm : subvector_zero_lowering<"DQAY", VR256, v8i64, v4i64, v16i32,
|
|
|
355 loadv4i64, sub_ymm>;
|
|
|
356 defm : subvector_zero_lowering<"DQAY", VR256, v16i32, v8i32, v16i32,
|
|
|
357 loadv4i64, sub_ymm>;
|
|
|
358 defm : subvector_zero_lowering<"DQAY", VR256, v32i16, v16i16, v16i32,
|
|
|
359 loadv4i64, sub_ymm>;
|
|
|
360 defm : subvector_zero_lowering<"DQAY", VR256, v64i8, v32i8, v16i32,
|
|
|
361 loadv4i64, sub_ymm>;
|
|
|
362 }
|
|
|
363
|
|
|
364 // List of opcodes that guaranteed to zero the upper elements of vector regs.
|
|
|
365 // TODO: Ideally this would be a blacklist instead of a whitelist. But SHA
|
|
|
366 // intrinsics and some MMX->XMM move instructions that aren't VEX encoded make
|
|
|
367 // this difficult. So starting with a couple opcodes used by reduction loops
|
|
|
368 // where we explicitly insert zeros.
|
|
|
369 class veczeroupper<ValueType vt, RegisterClass RC> :
|
|
|
370 PatLeaf<(vt RC:$src), [{
|
|
|
371 return N->getOpcode() == X86ISD::VPMADDWD ||
|
|
|
372 N->getOpcode() == X86ISD::PSADBW;
|
|
|
373 }]>;
|
|
|
374
|
|
|
375 def zeroupperv2f64 : veczeroupper<v2f64, VR128>;
|
|
|
376 def zeroupperv4f32 : veczeroupper<v4f32, VR128>;
|
|
|
377 def zeroupperv2i64 : veczeroupper<v2i64, VR128>;
|
|
|
378 def zeroupperv4i32 : veczeroupper<v4i32, VR128>;
|
|
|
379 def zeroupperv8i16 : veczeroupper<v8i16, VR128>;
|
|
|
380 def zeroupperv16i8 : veczeroupper<v16i8, VR128>;
|
|
|
381
|
|
|
382 def zeroupperv4f64 : veczeroupper<v4f64, VR256>;
|
|
|
383 def zeroupperv8f32 : veczeroupper<v8f32, VR256>;
|
|
|
384 def zeroupperv4i64 : veczeroupper<v4i64, VR256>;
|
|
|
385 def zeroupperv8i32 : veczeroupper<v8i32, VR256>;
|
|
|
386 def zeroupperv16i16 : veczeroupper<v16i16, VR256>;
|
|
|
387 def zeroupperv32i8 : veczeroupper<v32i8, VR256>;
|
|
|
388
|
|
|
389
|
|
|
390 // If we can guarantee the upper elements have already been zeroed we can elide
|
|
|
391 // an explicit zeroing.
|
|
|
392 multiclass subvector_zero_ellision<RegisterClass RC, ValueType DstTy,
|
|
|
393 ValueType SrcTy, ValueType ZeroTy,
|
|
|
394 SubRegIndex SubIdx, PatLeaf Zeroupper> {
|
|
|
395 def : Pat<(DstTy (insert_subvector (bitconvert (ZeroTy immAllZerosV)),
|
|
|
396 Zeroupper:$src, (iPTR 0))),
|
|
|
397 (SUBREG_TO_REG (i64 0), RC:$src, SubIdx)>;
|
|
|
398 }
|
|
|
399
|
|
|
400 // 128->256
|
|
|
401 defm: subvector_zero_ellision<VR128, v4f64, v2f64, v8i32, sub_xmm, zeroupperv2f64>;
|
|
|
402 defm: subvector_zero_ellision<VR128, v8f32, v4f32, v8i32, sub_xmm, zeroupperv4f32>;
|
|
|
403 defm: subvector_zero_ellision<VR128, v4i64, v2i64, v8i32, sub_xmm, zeroupperv2i64>;
|
|
|
404 defm: subvector_zero_ellision<VR128, v8i32, v4i32, v8i32, sub_xmm, zeroupperv4i32>;
|
|
|
405 defm: subvector_zero_ellision<VR128, v16i16, v8i16, v8i32, sub_xmm, zeroupperv8i16>;
|
|
|
406 defm: subvector_zero_ellision<VR128, v32i8, v16i8, v8i32, sub_xmm, zeroupperv16i8>;
|
|
|
407
|
|
|
408 // 128->512
|
|
|
409 defm: subvector_zero_ellision<VR128, v8f64, v2f64, v16i32, sub_xmm, zeroupperv2f64>;
|
|
|
410 defm: subvector_zero_ellision<VR128, v16f32, v4f32, v16i32, sub_xmm, zeroupperv4f32>;
|
|
|
411 defm: subvector_zero_ellision<VR128, v8i64, v2i64, v16i32, sub_xmm, zeroupperv2i64>;
|
|
|
412 defm: subvector_zero_ellision<VR128, v16i32, v4i32, v16i32, sub_xmm, zeroupperv4i32>;
|
|
|
413 defm: subvector_zero_ellision<VR128, v32i16, v8i16, v16i32, sub_xmm, zeroupperv8i16>;
|
|
|
414 defm: subvector_zero_ellision<VR128, v64i8, v16i8, v16i32, sub_xmm, zeroupperv16i8>;
|
|
|
415
|
|
|
416 // 256->512
|
|
|
417 defm: subvector_zero_ellision<VR256, v8f64, v4f64, v16i32, sub_ymm, zeroupperv4f64>;
|
|
|
418 defm: subvector_zero_ellision<VR256, v16f32, v8f32, v16i32, sub_ymm, zeroupperv8f32>;
|
|
|
419 defm: subvector_zero_ellision<VR256, v8i64, v4i64, v16i32, sub_ymm, zeroupperv4i64>;
|
|
|
420 defm: subvector_zero_ellision<VR256, v16i32, v8i32, v16i32, sub_ymm, zeroupperv8i32>;
|
|
|
421 defm: subvector_zero_ellision<VR256, v32i16, v16i16, v16i32, sub_ymm, zeroupperv16i16>;
|
|
|
422 defm: subvector_zero_ellision<VR256, v64i8, v32i8, v16i32, sub_ymm, zeroupperv32i8>;
|
|
|
423
|
|
|
424
|
|
|
425 class maskzeroupper<ValueType vt, RegisterClass RC> :
|
|
|
426 PatLeaf<(vt RC:$src), [{
|
|
|
427 return isMaskZeroExtended(N);
|
|
|
428 }]>;
|
|
|
429
|
|
|
430 def maskzeroupperv2i1 : maskzeroupper<v2i1, VK2>;
|
|
|
431 def maskzeroupperv4i1 : maskzeroupper<v4i1, VK4>;
|
|
|
432 def maskzeroupperv8i1 : maskzeroupper<v8i1, VK8>;
|
|
|
433 def maskzeroupperv16i1 : maskzeroupper<v16i1, VK16>;
|
|
|
434 def maskzeroupperv32i1 : maskzeroupper<v32i1, VK32>;
|
|
|
435
|
|
|
436 // The patterns determine if we can depend on the upper bits of a mask register
|
|
|
437 // being zeroed by the previous operation so that we can skip explicit
|
|
|
438 // zeroing.
|
|
|
439 let Predicates = [HasBWI] in {
|
|
|
440 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
|
|
|
441 maskzeroupperv8i1:$src, (iPTR 0))),
|
|
|
442 (COPY_TO_REGCLASS VK8:$src, VK32)>;
|
|
|
443 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
|
|
|
444 maskzeroupperv16i1:$src, (iPTR 0))),
|
|
|
445 (COPY_TO_REGCLASS VK16:$src, VK32)>;
|
|
|
446 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
|
|
|
447 maskzeroupperv8i1:$src, (iPTR 0))),
|
|
|
448 (COPY_TO_REGCLASS VK8:$src, VK64)>;
|
|
|
449 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
|
|
|
450 maskzeroupperv16i1:$src, (iPTR 0))),
|
|
|
451 (COPY_TO_REGCLASS VK16:$src, VK64)>;
|
|
|
452 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
|
|
|
453 maskzeroupperv32i1:$src, (iPTR 0))),
|
|
|
454 (COPY_TO_REGCLASS VK32:$src, VK64)>;
|
|
|
455 }
|
|
|
456
|
|
|
457 let Predicates = [HasAVX512] in {
|
|
|
458 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
|
|
|
459 maskzeroupperv8i1:$src, (iPTR 0))),
|
|
|
460 (COPY_TO_REGCLASS VK8:$src, VK16)>;
|
|
|
461 }
|
|
|
462
|
|
|
463 let Predicates = [HasVLX] in {
|
|
|
464 def : Pat<(v4i1 (insert_subvector (v4i1 immAllZerosV),
|
|
|
465 maskzeroupperv2i1:$src, (iPTR 0))),
|
|
|
466 (COPY_TO_REGCLASS VK2:$src, VK4)>;
|
|
|
467 def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV),
|
|
|
468 maskzeroupperv2i1:$src, (iPTR 0))),
|
|
|
469 (COPY_TO_REGCLASS VK2:$src, VK8)>;
|
|
|
470 def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV),
|
|
|
471 maskzeroupperv4i1:$src, (iPTR 0))),
|
|
|
472 (COPY_TO_REGCLASS VK4:$src, VK8)>;
|
|
|
473 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
|
|
|
474 maskzeroupperv2i1:$src, (iPTR 0))),
|
|
|
475 (COPY_TO_REGCLASS VK2:$src, VK16)>;
|
|
|
476 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
|
|
|
477 maskzeroupperv4i1:$src, (iPTR 0))),
|
|
|
478 (COPY_TO_REGCLASS VK4:$src, VK16)>;
|
|
|
479 }
|
|
|
480
|
|
|
481 let Predicates = [HasBWI, HasVLX] in {
|
|
|
482 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
|
|
|
483 maskzeroupperv2i1:$src, (iPTR 0))),
|
|
|
484 (COPY_TO_REGCLASS VK2:$src, VK32)>;
|
|
|
485 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
|
|
|
486 maskzeroupperv4i1:$src, (iPTR 0))),
|
|
|
487 (COPY_TO_REGCLASS VK4:$src, VK32)>;
|
|
|
488 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
|
|
|
489 maskzeroupperv2i1:$src, (iPTR 0))),
|
|
|
490 (COPY_TO_REGCLASS VK2:$src, VK64)>;
|
|
|
491 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
|
|
|
492 maskzeroupperv4i1:$src, (iPTR 0))),
|
|
|
493 (COPY_TO_REGCLASS VK4:$src, VK64)>;
|
|
|
494 }
|
|
|
495
|
|
|
496 // If the bits are not zero we have to fall back to explicitly zeroing by
|
|
|
497 // using shifts.
|
|
|
498 let Predicates = [HasAVX512, NoVLX] in {
|
|
|
499 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
|
|
|
500 (v8i1 VK8:$mask), (iPTR 0))),
|
|
|
501 (KSHIFTRWri (KSHIFTLWri (COPY_TO_REGCLASS VK8:$mask, VK16),
|
|
|
502 (i8 8)), (i8 8))>;
|
|
|
503 }
|
