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annotate test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll @ 0:95c75e76d11b

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LLVM 3.4
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Thu, 12 Dec 2013 13:56:28 +0900
parents
children afa8332a0e37
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95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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1 ; RUN: llc < %s -o /dev/null "-mtriple=thumbv7-apple-ios" -debug-only=post-RA-sched 2> %t
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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2 ; RUN: FileCheck %s < %t
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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3 ; REQUIRES: asserts
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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4 ; Make sure that mayalias store-load dependencies have one cycle
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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5 ; latency regardless of whether they are barriers or not.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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6
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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7 ; CHECK: ** List Scheduling
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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8 ; CHECK: SU(2){{.*}}STR{{.*}}Volatile
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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9 ; CHECK-NOT: ch SU
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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10 ; CHECK: ch SU(3): Latency=1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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11 ; CHECK-NOT: ch SU
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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12 ; CHECK: SU(3){{.*}}LDR{{.*}}Volatile
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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13 ; CHECK-NOT: ch SU
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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14 ; CHECK: ch SU(2): Latency=1
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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15 ; CHECK-NOT: ch SU
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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16 ; CHECK: Successors:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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17 ; CHECK: ** List Scheduling
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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18 ; CHECK: SU(2){{.*}}STR{{.*}}
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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19 ; CHECK-NOT: ch SU
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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20 ; CHECK: ch SU(3): Latency=1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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21 ; CHECK-NOT: ch SU
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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22 ; CHECK: SU(3){{.*}}LDR{{.*}}
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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23 ; CHECK-NOT: ch SU
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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24 ; CHECK: ch SU(2): Latency=1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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25 ; CHECK-NOT: ch SU
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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26 ; CHECK: Successors:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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27 define i32 @f1(i32* nocapture %p1, i32* nocapture %p2) nounwind {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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28 entry:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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29 store volatile i32 65540, i32* %p1, align 4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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30 %0 = load volatile i32* %p2, align 4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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31 ret i32 %0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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32 }
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33
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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34 define i32 @f2(i32* nocapture %p1, i32* nocapture %p2) nounwind {
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35 entry:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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36 store i32 65540, i32* %p1, align 4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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37 %0 = load i32* %p2, align 4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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38 ret i32 %0
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39 }