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121
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1 //===- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map -----------------===//
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2 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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3 // The LLVM Compiler Infrastructure
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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4 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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5 // This file is distributed under the University of Illinois Open Source
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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6 // License. See LICENSE.TXT for details.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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7 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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8 //===----------------------------------------------------------------------===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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9 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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10 // This file implements the VirtRegMap class.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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11 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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12 // It also contains implementations of the Spiller interface, which, given a
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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13 // virtual register map and a machine function, eliminates all virtual
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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14 // references by replacing them with physical register references - adding spill
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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15 // code as necessary.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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16 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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17 //===----------------------------------------------------------------------===//
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18
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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19 #include "llvm/CodeGen/VirtRegMap.h"
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20 #include "LiveDebugVariables.h"
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121
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21 #include "llvm/ADT/SmallVector.h"
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22 #include "llvm/ADT/Statistic.h"
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121
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23 #include "llvm/CodeGen/LiveInterval.h"
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24 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
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25 #include "llvm/CodeGen/LiveStackAnalysis.h"
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121
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26 #include "llvm/CodeGen/MachineBasicBlock.h"
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27 #include "llvm/CodeGen/MachineFrameInfo.h"
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28 #include "llvm/CodeGen/MachineFunction.h"
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121
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29 #include "llvm/CodeGen/MachineFunctionPass.h"
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30 #include "llvm/CodeGen/MachineInstr.h"
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31 #include "llvm/CodeGen/MachineOperand.h"
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32 #include "llvm/CodeGen/MachineRegisterInfo.h"
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121
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33 #include "llvm/CodeGen/SlotIndexes.h"
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34 #include "llvm/MC/LaneBitmask.h"
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35 #include "llvm/Pass.h"
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36 #include "llvm/Support/Compiler.h"
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37 #include "llvm/Support/Debug.h"
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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38 #include "llvm/Support/raw_ostream.h"
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39 #include "llvm/Target/TargetInstrInfo.h"
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121
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40 #include "llvm/Target/TargetOpcodes.h"
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41 #include "llvm/Target/TargetRegisterInfo.h"
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77
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42 #include "llvm/Target/TargetSubtargetInfo.h"
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121
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43 #include <cassert>
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44 #include <iterator>
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45 #include <utility>
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46
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47 using namespace llvm;
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48
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77
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49 #define DEBUG_TYPE "regalloc"
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50
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51 STATISTIC(NumSpillSlots, "Number of spill slots allocated");
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52 STATISTIC(NumIdCopies, "Number of identity moves eliminated after rewriting");
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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53
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54 //===----------------------------------------------------------------------===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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55 // VirtRegMap implementation
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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56 //===----------------------------------------------------------------------===//
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57
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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58 char VirtRegMap::ID = 0;
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59
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60 INITIALIZE_PASS(VirtRegMap, "virtregmap", "Virtual Register Map", false, false)
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61
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62 bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
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63 MRI = &mf.getRegInfo();
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77
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64 TII = mf.getSubtarget().getInstrInfo();
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65 TRI = mf.getSubtarget().getRegisterInfo();
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66 MF = &mf;
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67
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68 Virt2PhysMap.clear();
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69 Virt2StackSlotMap.clear();
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70 Virt2SplitMap.clear();
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71
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72 grow();
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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73 return false;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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74 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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75
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76 void VirtRegMap::grow() {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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77 unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
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78 Virt2PhysMap.resize(NumRegs);
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79 Virt2StackSlotMap.resize(NumRegs);
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80 Virt2SplitMap.resize(NumRegs);
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81 }
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82
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121
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83 void VirtRegMap::assignVirt2Phys(unsigned virtReg, MCPhysReg physReg) {
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84 assert(TargetRegisterInfo::isVirtualRegister(virtReg) &&
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85 TargetRegisterInfo::isPhysicalRegister(physReg));
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86 assert(Virt2PhysMap[virtReg] == NO_PHYS_REG &&
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87 "attempt to assign physical register to already mapped "
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88 "virtual register");
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89 assert(!getRegInfo().isReserved(physReg) &&
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90 "Attempt to map virtReg to a reserved physReg");
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91 Virt2PhysMap[virtReg] = physReg;
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92 }
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93
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94 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
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121
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95 unsigned Size = TRI->getSpillSize(*RC);
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96 unsigned Align = TRI->getSpillAlignment(*RC);
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97 int SS = MF->getFrameInfo().CreateSpillStackObject(Size, Align);
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98 ++NumSpillSlots;
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99 return SS;
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100 }
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101
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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102 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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103 unsigned Hint = MRI->getSimpleHint(VirtReg);
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104 if (!Hint)
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120
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105 return false;
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106 if (TargetRegisterInfo::isVirtualRegister(Hint))
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107 Hint = getPhys(Hint);
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108 return getPhys(VirtReg) == Hint;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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109 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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110
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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111 bool VirtRegMap::hasKnownPreference(unsigned VirtReg) {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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112 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg);
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113 if (TargetRegisterInfo::isPhysicalRegister(Hint.second))
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114 return true;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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115 if (TargetRegisterInfo::isVirtualRegister(Hint.second))
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116 return hasPhys(Hint.second);
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117 return false;
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118 }
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119
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120 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
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121 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
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122 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
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123 "attempt to assign stack slot to already spilled register");
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124 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
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125 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
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126 }
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127
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128 void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
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129 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
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130 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
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131 "attempt to assign stack slot to already spilled register");
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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132 assert((SS >= 0 ||
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120
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133 (SS >= MF->getFrameInfo().getObjectIndexBegin())) &&
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134 "illegal fixed frame index");
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135 Virt2StackSlotMap[virtReg] = SS;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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136 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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137
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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138 void VirtRegMap::print(raw_ostream &OS, const Module*) const {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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139 OS << "********** REGISTER MAP **********\n";
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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140 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
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141 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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142 if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
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143 OS << '[' << PrintReg(Reg, TRI) << " -> "
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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144 << PrintReg(Virt2PhysMap[Reg], TRI) << "] "
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83
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145 << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
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146 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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147 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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148
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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149 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
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150 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
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151 if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
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152 OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
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83
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153 << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
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154 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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155 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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156 OS << '\n';
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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157 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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158
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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159 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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120
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160 LLVM_DUMP_METHOD void VirtRegMap::dump() const {
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161 print(dbgs());
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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162 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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163 #endif
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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164
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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165 //===----------------------------------------------------------------------===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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166 // VirtRegRewriter
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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167 //===----------------------------------------------------------------------===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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168 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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169 // The VirtRegRewriter is the last of the register allocator passes.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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170 // It rewrites virtual registers to physical registers as specified in the
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
171 // VirtRegMap analysis. It also updates live-in information on basic blocks
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
172 // according to LiveIntervals.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
173 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
174 namespace {
|
|
121
|
175
|
0
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|
176 class VirtRegRewriter : public MachineFunctionPass {
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177 MachineFunction *MF;
|
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|
178 const TargetRegisterInfo *TRI;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
179 const TargetInstrInfo *TII;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
180 MachineRegisterInfo *MRI;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
181 SlotIndexes *Indexes;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
182 LiveIntervals *LIS;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
183 VirtRegMap *VRM;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
184
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
185 void rewrite();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
186 void addMBBLiveIns();
|
|
95
|
187 bool readsUndefSubreg(const MachineOperand &MO) const;
|
|
|
188 void addLiveInsForSubRanges(const LiveInterval &LI, unsigned PhysReg) const;
|
|
120
|
189 void handleIdentityCopy(MachineInstr &MI) const;
|
|
121
|
190 void expandCopyBundle(MachineInstr &MI) const;
|
|
|
191 bool subRegLiveThrough(const MachineInstr &MI, unsigned SuperPhysReg) const;
|
|
95
|
192
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|
193 public:
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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194 static char ID;
|
|
121
|
195
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|
196 VirtRegRewriter() : MachineFunctionPass(ID) {}
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|
197
|
|
77
|
198 void getAnalysisUsage(AnalysisUsage &AU) const override;
|
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199
|
|
77
|
200 bool runOnMachineFunction(MachineFunction&) override;
|
|
121
|
201
|
|
120
|
202 MachineFunctionProperties getSetProperties() const override {
|
|
|
203 return MachineFunctionProperties().set(
|
|
|
204 MachineFunctionProperties::Property::NoVRegs);
|
|
|
205 }
|
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
206 };
|
|
121
|
207
|
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|
208 } // end anonymous namespace
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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209
|
|
121
|
210 char VirtRegRewriter::ID = 0;
|
|
|
211
|
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212 char &llvm::VirtRegRewriterID = VirtRegRewriter::ID;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
213
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
214 INITIALIZE_PASS_BEGIN(VirtRegRewriter, "virtregrewriter",
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
215 "Virtual Register Rewriter", false, false)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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216 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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217 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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218 INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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219 INITIALIZE_PASS_DEPENDENCY(LiveStacks)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
220 INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
221 INITIALIZE_PASS_END(VirtRegRewriter, "virtregrewriter",
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
222 "Virtual Register Rewriter", false, false)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
223
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
224 void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
225 AU.setPreservesCFG();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
226 AU.addRequired<LiveIntervals>();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
227 AU.addRequired<SlotIndexes>();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
228 AU.addPreserved<SlotIndexes>();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
229 AU.addRequired<LiveDebugVariables>();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
230 AU.addRequired<LiveStacks>();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
231 AU.addPreserved<LiveStacks>();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
232 AU.addRequired<VirtRegMap>();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
233 MachineFunctionPass::getAnalysisUsage(AU);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
234 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
235
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
236 bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
237 MF = &fn;
|
|
83
|
238 TRI = MF->getSubtarget().getRegisterInfo();
|
|
|
239 TII = MF->getSubtarget().getInstrInfo();
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
240 MRI = &MF->getRegInfo();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
241 Indexes = &getAnalysis<SlotIndexes>();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
242 LIS = &getAnalysis<LiveIntervals>();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
243 VRM = &getAnalysis<VirtRegMap>();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
244 DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
245 << "********** Function: "
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
246 << MF->getName() << '\n');
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
247 DEBUG(VRM->dump());
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
248
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
249 // Add kill flags while we still have virtual registers.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
250 LIS->addKillFlags(VRM);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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diff
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|
251
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
252 // Live-in lists on basic blocks are required for physregs.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
253 addMBBLiveIns();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
254
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
255 // Rewrite virtual registers.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
256 rewrite();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
257
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
258 // Write out new DBG_VALUE instructions.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
259 getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
260
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
261 // All machine operands and other references to virtual registers have been
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
262 // replaced. Remove the virtual registers and release all the transient data.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
263 VRM->clearAllVirt();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
264 MRI->clearVirtRegs();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
265 return true;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
266 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
267
|
|
95
|
268 void VirtRegRewriter::addLiveInsForSubRanges(const LiveInterval &LI,
|
|
|
269 unsigned PhysReg) const {
|
|
|
270 assert(!LI.empty());
|
|
|
271 assert(LI.hasSubRanges());
|
|
|
272
|
|
121
|
273 using SubRangeIteratorPair =
|
|
|
274 std::pair<const LiveInterval::SubRange *, LiveInterval::const_iterator>;
|
|
|
275
|
|
95
|
276 SmallVector<SubRangeIteratorPair, 4> SubRanges;
|
|
|
277 SlotIndex First;
|
|
|
278 SlotIndex Last;
|
|
|
279 for (const LiveInterval::SubRange &SR : LI.subranges()) {
|
|
|
280 SubRanges.push_back(std::make_pair(&SR, SR.begin()));
|
|
|
281 if (!First.isValid() || SR.segments.front().start < First)
|
|
|
282 First = SR.segments.front().start;
|
|
|
283 if (!Last.isValid() || SR.segments.back().end > Last)
|
|
|
284 Last = SR.segments.back().end;
|
|
|
285 }
|
|
|
286
|
|
|
287 // Check all mbb start positions between First and Last while
|
|
|
288 // simulatenously advancing an iterator for each subrange.
|
|
|
289 for (SlotIndexes::MBBIndexIterator MBBI = Indexes->findMBBIndex(First);
|
|
|
290 MBBI != Indexes->MBBIndexEnd() && MBBI->first <= Last; ++MBBI) {
|
|
|
291 SlotIndex MBBBegin = MBBI->first;
|
|
|
292 // Advance all subrange iterators so that their end position is just
|
|
|
293 // behind MBBBegin (or the iterator is at the end).
|
|
121
|
294 LaneBitmask LaneMask;
|
|
95
|
295 for (auto &RangeIterPair : SubRanges) {
|
|
|
296 const LiveInterval::SubRange *SR = RangeIterPair.first;
|
|
|
297 LiveInterval::const_iterator &SRI = RangeIterPair.second;
|
|
|
298 while (SRI != SR->end() && SRI->end <= MBBBegin)
|
|
|
299 ++SRI;
|
|
|
300 if (SRI == SR->end())
|
|
|
301 continue;
|
|
|
302 if (SRI->start <= MBBBegin)
|
|
|
303 LaneMask |= SR->LaneMask;
|
|
|
304 }
|
|
121
|
305 if (LaneMask.none())
|
|
95
|
306 continue;
|
|
|
307 MachineBasicBlock *MBB = MBBI->second;
|
|
|
308 MBB->addLiveIn(PhysReg, LaneMask);
|
|
|
309 }
|
|
|
310 }
|
|
|
311
|
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
312 // Compute MBB live-in lists from virtual register live ranges and their
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
313 // assignments.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
314 void VirtRegRewriter::addMBBLiveIns() {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
315 for (unsigned Idx = 0, IdxE = MRI->getNumVirtRegs(); Idx != IdxE; ++Idx) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
316 unsigned VirtReg = TargetRegisterInfo::index2VirtReg(Idx);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
317 if (MRI->reg_nodbg_empty(VirtReg))
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
318 continue;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
319 LiveInterval &LI = LIS->getInterval(VirtReg);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
320 if (LI.empty() || LIS->intervalIsInOneMBB(LI))
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
321 continue;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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changeset
|
322 // This is a virtual register that is live across basic blocks. Its
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
323 // assigned PhysReg must be marked as live-in to those blocks.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
324 unsigned PhysReg = VRM->getPhys(VirtReg);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
325 assert(PhysReg != VirtRegMap::NO_PHYS_REG && "Unmapped virtual register.");
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
326
|
|
83
|
327 if (LI.hasSubRanges()) {
|
|
95
|
328 addLiveInsForSubRanges(LI, PhysReg);
|
|
|
329 } else {
|
|
|
330 // Go over MBB begin positions and see if we have segments covering them.
|
|
|
331 // The following works because segments and the MBBIndex list are both
|
|
|
332 // sorted by slot indexes.
|
|
|
333 SlotIndexes::MBBIndexIterator I = Indexes->MBBIndexBegin();
|
|
|
334 for (const auto &Seg : LI) {
|
|
|
335 I = Indexes->advanceMBBIndex(I, Seg.start);
|
|
|
336 for (; I != Indexes->MBBIndexEnd() && I->first < Seg.end; ++I) {
|
|
|
337 MachineBasicBlock *MBB = I->second;
|
|
|
338 MBB->addLiveIn(PhysReg);
|
|
83
|
339 }
|
|
|
340 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
341 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
342 }
|
|
95
|
343
|
|
|
344 // Sort and unique MBB LiveIns as we've not checked if SubReg/PhysReg were in
|
|
|
345 // each MBB's LiveIns set before calling addLiveIn on them.
|
|
|
346 for (MachineBasicBlock &MBB : *MF)
|
|
|
347 MBB.sortUniqueLiveIns();
|
|
|
348 }
|
|
|
349
|
|
|
350 /// Returns true if the given machine operand \p MO only reads undefined lanes.
|
|
|
351 /// The function only works for use operands with a subregister set.
|
|
|
352 bool VirtRegRewriter::readsUndefSubreg(const MachineOperand &MO) const {
|
|
|
353 // Shortcut if the operand is already marked undef.
|
|
|
354 if (MO.isUndef())
|
|
|
355 return true;
|
|
|
356
|
|
|
357 unsigned Reg = MO.getReg();
|
|
|
358 const LiveInterval &LI = LIS->getInterval(Reg);
|
|
|
359 const MachineInstr &MI = *MO.getParent();
|
|
120
|
360 SlotIndex BaseIndex = LIS->getInstructionIndex(MI);
|
|
95
|
361 // This code is only meant to handle reading undefined subregisters which
|
|
|
362 // we couldn't properly detect before.
|
|
|
363 assert(LI.liveAt(BaseIndex) &&
|
|
|
364 "Reads of completely dead register should be marked undef already");
|
|
|
365 unsigned SubRegIdx = MO.getSubReg();
|
|
120
|
366 assert(SubRegIdx != 0 && LI.hasSubRanges());
|
|
95
|
367 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx);
|
|
|
368 // See if any of the relevant subregister liveranges is defined at this point.
|
|
|
369 for (const LiveInterval::SubRange &SR : LI.subranges()) {
|
|
121
|
370 if ((SR.LaneMask & UseMask).any() && SR.liveAt(BaseIndex))
|
|
95
|
371 return false;
|
|
|
372 }
|
|
|
373 return true;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
374 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
375
|
|
120
|
376 void VirtRegRewriter::handleIdentityCopy(MachineInstr &MI) const {
|
|
|
377 if (!MI.isIdentityCopy())
|
|
|
378 return;
|
|
|
379 DEBUG(dbgs() << "Identity copy: " << MI);
|
|
|
380 ++NumIdCopies;
|
|
|
381
|
|
|
382 // Copies like:
|
|
|
383 // %R0 = COPY %R0<undef>
|
|
|
384 // %AL = COPY %AL, %EAX<imp-def>
|
|
|
385 // give us additional liveness information: The target (super-)register
|
|
|
386 // must not be valid before this point. Replace the COPY with a KILL
|
|
|
387 // instruction to maintain this information.
|
|
|
388 if (MI.getOperand(0).isUndef() || MI.getNumOperands() > 2) {
|
|
|
389 MI.setDesc(TII->get(TargetOpcode::KILL));
|
|
|
390 DEBUG(dbgs() << " replace by: " << MI);
|
|
|
391 return;
|
|
|
392 }
|
|
|
393
|
|
|
394 if (Indexes)
|
|
121
|
395 Indexes->removeSingleMachineInstrFromMaps(MI);
|
|
|
396 MI.eraseFromBundle();
|
|
120
|
397 DEBUG(dbgs() << " deleted.\n");
|
|
|
398 }
|
|
|
399
|
|
121
|
400 /// The liverange splitting logic sometimes produces bundles of copies when
|
|
|
401 /// subregisters are involved. Expand these into a sequence of copy instructions
|
|
|
402 /// after processing the last in the bundle. Does not update LiveIntervals
|
|
|
403 /// which we shouldn't need for this instruction anymore.
|
|
|
404 void VirtRegRewriter::expandCopyBundle(MachineInstr &MI) const {
|
|
|
405 if (!MI.isCopy())
|
|
|
406 return;
|
|
|
407
|
|
|
408 if (MI.isBundledWithPred() && !MI.isBundledWithSucc()) {
|
|
|
409 // Only do this when the complete bundle is made out of COPYs.
|
|
|
410 MachineBasicBlock &MBB = *MI.getParent();
|
|
|
411 for (MachineBasicBlock::reverse_instr_iterator I =
|
|
|
412 std::next(MI.getReverseIterator()), E = MBB.instr_rend();
|
|
|
413 I != E && I->isBundledWithSucc(); ++I) {
|
|
|
414 if (!I->isCopy())
|
|
|
415 return;
|
|
|
416 }
|
|
|
417
|
|
|
418 for (MachineBasicBlock::reverse_instr_iterator I = MI.getReverseIterator();
|
|
|
419 I->isBundledWithPred(); ) {
|
|
|
420 MachineInstr &MI = *I;
|
|
|
421 ++I;
|
|
|
422
|
|
|
423 MI.unbundleFromPred();
|
|
|
424 if (Indexes)
|
|
|
425 Indexes->insertMachineInstrInMaps(MI);
|
|
|
426 }
|
|
|
427 }
|
|
|
428 }
|
|
|
429
|
|
|
430 /// Check whether (part of) \p SuperPhysReg is live through \p MI.
|
|
|
431 /// \pre \p MI defines a subregister of a virtual register that
|
|
|
432 /// has been assigned to \p SuperPhysReg.
|
|
|
433 bool VirtRegRewriter::subRegLiveThrough(const MachineInstr &MI,
|
|
|
434 unsigned SuperPhysReg) const {
|
|
|
435 SlotIndex MIIndex = LIS->getInstructionIndex(MI);
|
|
|
436 SlotIndex BeforeMIUses = MIIndex.getBaseIndex();
|
|
|
437 SlotIndex AfterMIDefs = MIIndex.getBoundaryIndex();
|
|
|
438 for (MCRegUnitIterator Unit(SuperPhysReg, TRI); Unit.isValid(); ++Unit) {
|
|
|
439 const LiveRange &UnitRange = LIS->getRegUnit(*Unit);
|
|
|
440 // If the regunit is live both before and after MI,
|
|
|
441 // we assume it is live through.
|
|
|
442 // Generally speaking, this is not true, because something like
|
|
|
443 // "RU = op RU" would match that description.
|
|
|
444 // However, we know that we are trying to assess whether
|
|
|
445 // a def of a virtual reg, vreg, is live at the same time of RU.
|
|
|
446 // If we are in the "RU = op RU" situation, that means that vreg
|
|
|
447 // is defined at the same time as RU (i.e., "vreg, RU = op RU").
|
|
|
448 // Thus, vreg and RU interferes and vreg cannot be assigned to
|
|
|
449 // SuperPhysReg. Therefore, this situation cannot happen.
|
|
|
450 if (UnitRange.liveAt(AfterMIDefs) && UnitRange.liveAt(BeforeMIUses))
|
|
|
451 return true;
|
|
|
452 }
|
|
|
453 return false;
|
|
|
454 }
|
|
|
455
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
456 void VirtRegRewriter::rewrite() {
|
|
95
|
457 bool NoSubRegLiveness = !MRI->subRegLivenessEnabled();
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
458 SmallVector<unsigned, 8> SuperDeads;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
459 SmallVector<unsigned, 8> SuperDefs;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
460 SmallVector<unsigned, 8> SuperKills;
|
|
77
|
461
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
462 for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
463 MBBI != MBBE; ++MBBI) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
464 DEBUG(MBBI->print(dbgs(), Indexes));
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
465 for (MachineBasicBlock::instr_iterator
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
466 MII = MBBI->instr_begin(), MIE = MBBI->instr_end(); MII != MIE;) {
|
|
95
|
467 MachineInstr *MI = &*MII;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
468 ++MII;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
469
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
470 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
471 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
472 MachineOperand &MO = *MOI;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
473
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
474 // Make sure MRI knows about registers clobbered by regmasks.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
475 if (MO.isRegMask())
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
476 MRI->addPhysRegsUsedFromRegMask(MO.getRegMask());
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
477
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
478 if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
479 continue;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
480 unsigned VirtReg = MO.getReg();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
481 unsigned PhysReg = VRM->getPhys(VirtReg);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
482 assert(PhysReg != VirtRegMap::NO_PHYS_REG &&
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
483 "Instruction uses unmapped VirtReg");
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
484 assert(!MRI->isReserved(PhysReg) && "Reserved register assignment");
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
485
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
486 // Preserve semantics of sub-register operands.
|
|
95
|
487 unsigned SubReg = MO.getSubReg();
|
|
|
488 if (SubReg != 0) {
|
|
|
489 if (NoSubRegLiveness) {
|
|
|
490 // A virtual register kill refers to the whole register, so we may
|
|
|
491 // have to add <imp-use,kill> operands for the super-register. A
|
|
|
492 // partial redef always kills and redefines the super-register.
|
|
121
|
493 if ((MO.readsReg() && (MO.isDef() || MO.isKill())) ||
|
|
|
494 (MO.isDef() && subRegLiveThrough(*MI, PhysReg)))
|
|
95
|
495 SuperKills.push_back(PhysReg);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
496
|
|
95
|
497 if (MO.isDef()) {
|
|
|
498 // Also add implicit defs for the super-register.
|
|
83
|
499 if (MO.isDead())
|
|
|
500 SuperDeads.push_back(PhysReg);
|
|
|
501 else
|
|
|
502 SuperDefs.push_back(PhysReg);
|
|
|
503 }
|
|
95
|
504 } else {
|
|
|
505 if (MO.isUse()) {
|
|
|
506 if (readsUndefSubreg(MO))
|
|
|
507 // We need to add an <undef> flag if the subregister is
|
|
|
508 // completely undefined (and we are not adding super-register
|
|
|
509 // defs).
|
|
|
510 MO.setIsUndef(true);
|
|
|
511 } else if (!MO.isDead()) {
|
|
|
512 assert(MO.isDef());
|
|
|
513 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
514 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
515
|
|
121
|
516 // The <def,undef> and <def,internal> flags only make sense for
|
|
|
517 // sub-register defs, and we are substituting a full physreg. An
|
|
|
518 // <imp-use,kill> operand from the SuperKills list will represent the
|
|
|
519 // partial read of the super-register.
|
|
|
520 if (MO.isDef()) {
|
|
95
|
521 MO.setIsUndef(false);
|
|
121
|
522 MO.setIsInternalRead(false);
|
|
|
523 }
|
|
95
|
524
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
525 // PhysReg operands cannot have subregister indexes.
|
|
95
|
526 PhysReg = TRI->getSubReg(PhysReg, SubReg);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
527 assert(PhysReg && "Invalid SubReg for physical register");
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
528 MO.setSubReg(0);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
529 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
530 // Rewrite. Note we could have used MachineOperand::substPhysReg(), but
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
531 // we need the inlining here.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
532 MO.setReg(PhysReg);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
533 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
534
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
535 // Add any missing super-register kills after rewriting the whole
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
536 // instruction.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
537 while (!SuperKills.empty())
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
538 MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
539
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
540 while (!SuperDeads.empty())
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
541 MI->addRegisterDead(SuperDeads.pop_back_val(), TRI, true);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
542
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
543 while (!SuperDefs.empty())
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
544 MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
545
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
546 DEBUG(dbgs() << "> " << *MI);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
547
|
|
121
|
548 expandCopyBundle(*MI);
|
|
|
549
|
|
120
|
550 // We can remove identity copies right now.
|
|
|
551 handleIdentityCopy(*MI);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
552 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
553 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
554 }
|
