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1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file contains the X86 implementation of the TargetInstrInfo class.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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77
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14 #ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H
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|
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15 #define LLVM_LIB_TARGET_X86_X86INSTRINFO_H
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16
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77
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17 #include "MCTargetDesc/X86BaseInfo.h"
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120
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18 #include "X86InstrFMA3Info.h"
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19 #include "X86RegisterInfo.h"
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20 #include "llvm/ADT/DenseMap.h"
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21 #include "llvm/Target/TargetInstrInfo.h"
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22
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23 #define GET_INSTRINFO_HEADER
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24 #include "X86GenInstrInfo.inc"
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25
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26 namespace llvm {
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121
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27 class MachineInstrBuilder;
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28 class X86RegisterInfo;
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29 class X86Subtarget;
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30
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31 namespace X86 {
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121
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32 // X86 specific condition code. These correspond to X86_*_COND in
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33 // X86InstrInfo.td. They must be kept in synch.
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120
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34 enum CondCode {
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35 COND_A = 0,
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36 COND_AE = 1,
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37 COND_B = 2,
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38 COND_BE = 3,
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39 COND_E = 4,
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40 COND_G = 5,
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41 COND_GE = 6,
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42 COND_L = 7,
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43 COND_LE = 8,
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44 COND_NE = 9,
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45 COND_NO = 10,
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46 COND_NP = 11,
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47 COND_NS = 12,
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48 COND_O = 13,
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49 COND_P = 14,
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50 COND_S = 15,
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51 LAST_VALID_COND = COND_S,
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52
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120
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53 // Artificial condition codes. These are used by AnalyzeBranch
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54 // to indicate a block terminated with two conditional branches that together
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55 // form a compound condition. They occur in code using FCMP_OEQ or FCMP_UNE,
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56 // which can't be represented on x86 with a single condition. These
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57 // are never used in MachineInstrs and are inverses of one another.
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58 COND_NE_OR_P,
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59 COND_E_AND_NP,
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60
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61 COND_INVALID
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62 };
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63
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120
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64 // Turn condition code into conditional branch opcode.
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65 unsigned GetCondBranchFromCond(CondCode CC);
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66
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121
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67 /// \brief Return a pair of condition code for the given predicate and whether
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68 /// the instruction operands should be swaped to match the condition code.
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69 std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate);
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70
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120
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71 /// \brief Return a set opcode for the given condition and whether it has
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72 /// a memory operand.
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73 unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand = false);
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77
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74
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120
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75 /// \brief Return a cmov opcode for the given condition, register size in
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76 /// bytes, and operand type.
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77 unsigned getCMovFromCond(CondCode CC, unsigned RegBytes,
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78 bool HasMemoryOperand = false);
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77
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79
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120
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80 // Turn CMov opcode into condition code.
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81 CondCode getCondFromCMovOpc(unsigned Opc);
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82
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120
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83 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
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84 /// e.g. turning COND_E to COND_NE.
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85 CondCode GetOppositeBranchCondition(CondCode CC);
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121
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86 } // namespace X86
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87
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88 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
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89 /// a reference to a stub for a global, not the global itself.
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90 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
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91 switch (TargetFlag) {
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121
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92 case X86II::MO_DLLIMPORT: // dllimport stub.
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93 case X86II::MO_GOTPCREL: // rip-relative GOT reference.
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94 case X86II::MO_GOT: // normal GOT reference.
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95 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
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96 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
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97 return true;
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98 default:
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99 return false;
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100 }
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101 }
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102
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103 /// isGlobalRelativeToPICBase - Return true if the specified global value
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104 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
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105 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
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106 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
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107 switch (TargetFlag) {
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121
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108 case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
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109 case X86II::MO_GOT: // isPICStyleGOT: other global.
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110 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
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111 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
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112 case X86II::MO_TLVP: // ??? Pretty sure..
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113 return true;
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114 default:
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115 return false;
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116 }
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117 }
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118
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119 inline static bool isScale(const MachineOperand &MO) {
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121
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120 return MO.isImm() && (MO.getImm() == 1 || MO.getImm() == 2 ||
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121 MO.getImm() == 4 || MO.getImm() == 8);
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122 }
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123
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120
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124 inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) {
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125 if (MI.getOperand(Op).isFI())
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126 return true;
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127 return Op + X86::AddrSegmentReg <= MI.getNumOperands() &&
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128 MI.getOperand(Op + X86::AddrBaseReg).isReg() &&
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129 isScale(MI.getOperand(Op + X86::AddrScaleAmt)) &&
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130 MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
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131 (MI.getOperand(Op + X86::AddrDisp).isImm() ||
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132 MI.getOperand(Op + X86::AddrDisp).isGlobal() ||
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133 MI.getOperand(Op + X86::AddrDisp).isCPI() ||
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134 MI.getOperand(Op + X86::AddrDisp).isJTI());
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135 }
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136
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120
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137 inline static bool isMem(const MachineInstr &MI, unsigned Op) {
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138 if (MI.getOperand(Op).isFI())
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139 return true;
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140 return Op + X86::AddrNumOperands <= MI.getNumOperands() &&
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141 MI.getOperand(Op + X86::AddrSegmentReg).isReg() && isLeaMem(MI, Op);
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142 }
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143
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144 class X86InstrInfo final : public X86GenInstrInfo {
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145 X86Subtarget &Subtarget;
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146 const X86RegisterInfo RI;
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147
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148 /// RegOp2MemOpTable3Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
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149 /// RegOp2MemOpTable2, RegOp2MemOpTable3 - Load / store folding opcode maps.
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150 ///
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121
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151 typedef DenseMap<unsigned, std::pair<uint16_t, uint16_t>>
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152 RegOp2MemOpTableType;
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153 RegOp2MemOpTableType RegOp2MemOpTable2Addr;
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154 RegOp2MemOpTableType RegOp2MemOpTable0;
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155 RegOp2MemOpTableType RegOp2MemOpTable1;
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156 RegOp2MemOpTableType RegOp2MemOpTable2;
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157 RegOp2MemOpTableType RegOp2MemOpTable3;
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83
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158 RegOp2MemOpTableType RegOp2MemOpTable4;
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159
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160 /// MemOp2RegOpTable - Load / store unfolding opcode map.
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161 ///
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121
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162 typedef DenseMap<unsigned, std::pair<uint16_t, uint16_t>>
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163 MemOp2RegOpTableType;
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164 MemOp2RegOpTableType MemOp2RegOpTable;
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165
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166 static void AddTableEntry(RegOp2MemOpTableType &R2MTable,
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121
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167 MemOp2RegOpTableType &M2RTable, uint16_t RegOp,
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168 uint16_t MemOp, uint16_t Flags);
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169
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170 virtual void anchor();
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171
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95
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172 bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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173 MachineBasicBlock *&FBB,
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174 SmallVectorImpl<MachineOperand> &Cond,
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175 SmallVectorImpl<MachineInstr *> &CondBranches,
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176 bool AllowModify) const;
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177
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178 public:
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179 explicit X86InstrInfo(X86Subtarget &STI);
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180
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181 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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182 /// such, whenever a client has an instance of instruction info, it should
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183 /// always be able to get register info as well (through this method).
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184 ///
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185 const X86RegisterInfo &getRegisterInfo() const { return RI; }
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186
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121
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187 /// Returns the stack pointer adjustment that happens inside the frame
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188 /// setup..destroy sequence (e.g. by pushes, or inside the callee).
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189 int64_t getFrameAdjustment(const MachineInstr &I) const {
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190 assert(isFrameInstr(I));
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191 if (isFrameSetup(I))
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192 return I.getOperand(2).getImm();
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193 return I.getOperand(1).getImm();
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194 }
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195
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196 /// Sets the stack pointer adjustment made inside the frame made up by this
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197 /// instruction.
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198 void setFrameAdjustment(MachineInstr &I, int64_t V) const {
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199 assert(isFrameInstr(I));
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200 if (isFrameSetup(I))
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201 I.getOperand(2).setImm(V);
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202 else
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203 I.getOperand(1).setImm(V);
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204 }
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205
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83
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206 /// getSPAdjust - This returns the stack pointer adjustment made by
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207 /// this instruction. For x86, we need to handle more complex call
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208 /// sequences involving PUSHes.
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120
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209 int getSPAdjust(const MachineInstr &MI) const override;
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83
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210
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211 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
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212 /// extension instruction. That is, it's like a copy where it's legal for the
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213 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
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214 /// true, then it's expected the pre-extension value is available as a subreg
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215 /// of the result register. This also returns the sub-register index in
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216 /// SubIdx.
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121
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217 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
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218 unsigned &DstReg, unsigned &SubIdx) const override;
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219
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120
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220 unsigned isLoadFromStackSlot(const MachineInstr &MI,
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77
|
221 int &FrameIndex) const override;
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222 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
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223 /// stack locations as well. This uses a heuristic so it isn't
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224 /// reliable for correctness.
|
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120
|
225 unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
|
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77
|
226 int &FrameIndex) const override;
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227
|
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120
|
228 unsigned isStoreToStackSlot(const MachineInstr &MI,
|
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77
|
229 int &FrameIndex) const override;
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230 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
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231 /// stack locations as well. This uses a heuristic so it isn't
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232 /// reliable for correctness.
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120
|
233 unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
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77
|
234 int &FrameIndex) const override;
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235
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120
|
236 bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
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77
|
237 AliasAnalysis *AA) const override;
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238 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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239 unsigned DestReg, unsigned SubIdx,
|
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120
|
240 const MachineInstr &Orig,
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77
|
241 const TargetRegisterInfo &TRI) const override;
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242
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243 /// Given an operand within a MachineInstr, insert preceding code to put it
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244 /// into the right format for a particular kind of LEA instruction. This may
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245 /// involve using an appropriate super-register instead (with an implicit use
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246 /// of the original) or creating a new virtual register and inserting COPY
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247 /// instructions to get the data into the right class.
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248 ///
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249 /// Reference parameters are set to indicate how caller should add this
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250 /// operand to the LEA instruction.
|
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120
|
251 bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
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|
|
252 unsigned LEAOpcode, bool AllowSP, unsigned &NewSrc,
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121
|
253 bool &isKill, bool &isUndef, MachineOperand &ImplicitOp,
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|
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254 LiveVariables *LV) const;
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255
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256 /// convertToThreeAddress - This method must be implemented by targets that
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257 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
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258 /// may be able to convert a two-address instruction into a true
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259 /// three-address instruction on demand. This allows the X86 target (for
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260 /// example) to convert ADD and SHL instructions into LEA instructions if they
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261 /// would require register copies due to two-addressness.
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262 ///
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263 /// This method returns a null pointer if the transformation cannot be
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264 /// performed, otherwise it returns the new instruction.
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265 ///
|
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77
|
266 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
|
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120
|
267 MachineInstr &MI,
|
|
77
|
268 LiveVariables *LV) const override;
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269
|
|
95
|
270 /// Returns true iff the routine could find two commutable operands in the
|
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271 /// given machine instruction.
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|
272 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
|
|
|
273 /// input values can be re-defined in this method only if the input values
|
|
|
274 /// are not pre-defined, which is designated by the special value
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|
275 /// 'CommuteAnyOperandIndex' assigned to it.
|
|
|
276 /// If both of indices are pre-defined and refer to some operands, then the
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|
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277 /// method simply returns true if the corresponding operands are commutable
|
|
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278 /// and returns false otherwise.
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279 ///
|
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95
|
280 /// For example, calling this method this way:
|
|
|
281 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
|
|
|
282 /// findCommutedOpIndices(MI, Op1, Op2);
|
|
|
283 /// can be interpreted as a query asking to find an operand that would be
|
|
|
284 /// commutable with the operand#1.
|
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120
|
285 bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
|
|
77
|
286 unsigned &SrcOpIdx2) const override;
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287
|
|
100
|
288 /// Returns true if the routine could find two commutable operands
|
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120
|
289 /// in the given FMA instruction \p MI. Otherwise, returns false.
|
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100
|
290 ///
|
|
|
291 /// \p SrcOpIdx1 and \p SrcOpIdx2 are INPUT and OUTPUT arguments.
|
|
|
292 /// The output indices of the commuted operands are returned in these
|
|
|
293 /// arguments. Also, the input values of these arguments may be preset either
|
|
|
294 /// to indices of operands that must be commuted or be equal to a special
|
|
|
295 /// value 'CommuteAnyOperandIndex' which means that the corresponding
|
|
|
296 /// operand index is not set and this method is free to pick any of
|
|
|
297 /// available commutable operands.
|
|
120
|
298 /// The parameter \p FMA3Group keeps the reference to the group of relative
|
|
|
299 /// FMA3 opcodes including register/memory forms of 132/213/231 opcodes.
|
|
100
|
300 ///
|
|
|
301 /// For example, calling this method this way:
|
|
|
302 /// unsigned Idx1 = 1, Idx2 = CommuteAnyOperandIndex;
|
|
120
|
303 /// findFMA3CommutedOpIndices(MI, Idx1, Idx2, FMA3Group);
|
|
100
|
304 /// can be interpreted as a query asking if the operand #1 can be swapped
|
|
|
305 /// with any other available operand (e.g. operand #2, operand #3, etc.).
|
|
|
306 ///
|
|
|
307 /// The returned FMA opcode may differ from the opcode in the given MI.
|
|
|
308 /// For example, commuting the operands #1 and #3 in the following FMA
|
|
|
309 /// FMA213 #1, #2, #3
|
|
|
310 /// results into instruction with adjusted opcode:
|
|
|
311 /// FMA231 #3, #2, #1
|
|
121
|
312 bool findFMA3CommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
|
|
120
|
313 unsigned &SrcOpIdx2,
|
|
|
314 const X86InstrFMA3Group &FMA3Group) const;
|
|
100
|
315
|
|
|
316 /// Returns an adjusted FMA opcode that must be used in FMA instruction that
|
|
120
|
317 /// performs the same computations as the given \p MI but which has the
|
|
|
318 /// operands \p SrcOpIdx1 and \p SrcOpIdx2 commuted.
|
|
100
|
319 /// It may return 0 if it is unsafe to commute the operands.
|
|
120
|
320 /// Note that a machine instruction (instead of its opcode) is passed as the
|
|
|
321 /// first parameter to make it possible to analyze the instruction's uses and
|
|
|
322 /// commute the first operand of FMA even when it seems unsafe when you look
|
|
|
323 /// at the opcode. For example, it is Ok to commute the first operand of
|
|
|
324 /// VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used.
|
|
100
|
325 ///
|
|
|
326 /// The returned FMA opcode may differ from the opcode in the given \p MI.
|
|
|
327 /// For example, commuting the operands #1 and #3 in the following FMA
|
|
|
328 /// FMA213 #1, #2, #3
|
|
|
329 /// results into instruction with adjusted opcode:
|
|
|
330 /// FMA231 #3, #2, #1
|
|
121
|
331 unsigned
|
|
|
332 getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1,
|
|
|
333 unsigned SrcOpIdx2,
|
|
|
334 const X86InstrFMA3Group &FMA3Group) const;
|
|
100
|
335
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336 // Branch analysis.
|
|
120
|
337 bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
|
|
|
338 bool isUnconditionalTailCall(const MachineInstr &MI) const override;
|
|
|
339 bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond,
|
|
|
340 const MachineInstr &TailCall) const override;
|
|
|
341 void replaceBranchWithTailCall(MachineBasicBlock &MBB,
|
|
|
342 SmallVectorImpl<MachineOperand> &Cond,
|
|
|
343 const MachineInstr &TailCall) const override;
|
|
|
344
|
|
|
345 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
|
|
77
|
346 MachineBasicBlock *&FBB,
|
|
|
347 SmallVectorImpl<MachineOperand> &Cond,
|
|
|
348 bool AllowModify) const override;
|
|
95
|
349
|
|
120
|
350 bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
|
|
|
351 int64_t &Offset,
|
|
95
|
352 const TargetRegisterInfo *TRI) const override;
|
|
120
|
353 bool analyzeBranchPredicate(MachineBasicBlock &MBB,
|
|
95
|
354 TargetInstrInfo::MachineBranchPredicate &MBP,
|
|
|
355 bool AllowModify = false) const override;
|
|
|
356
|
|
120
|
357 unsigned removeBranch(MachineBasicBlock &MBB,
|
|
|
358 int *BytesRemoved = nullptr) const override;
|
|
|
359 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
|
95
|
360 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
|
|
120
|
361 const DebugLoc &DL,
|
|
|
362 int *BytesAdded = nullptr) const override;
|
|
121
|
363 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
|
|
|
364 unsigned, unsigned, int &, int &, int &) const override;
|
|
120
|
365 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
|
|
366 const DebugLoc &DL, unsigned DstReg,
|
|
|
367 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
|
|
|
368 unsigned FalseReg) const override;
|
|
|
369 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
|
|
370 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
|
|
77
|
371 bool KillSrc) const override;
|
|
|
372 void storeRegToStackSlot(MachineBasicBlock &MBB,
|
|
121
|
373 MachineBasicBlock::iterator MI, unsigned SrcReg,
|
|
|
374 bool isKill, int FrameIndex,
|
|
77
|
375 const TargetRegisterClass *RC,
|
|
|
376 const TargetRegisterInfo *TRI) const override;
|
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|
377
|
|
77
|
378 void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
|
|
|
379 SmallVectorImpl<MachineOperand> &Addr,
|
|
|
380 const TargetRegisterClass *RC,
|
|
|
381 MachineInstr::mmo_iterator MMOBegin,
|
|
|
382 MachineInstr::mmo_iterator MMOEnd,
|
|
121
|
383 SmallVectorImpl<MachineInstr *> &NewMIs) const;
|
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|
384
|
|
77
|
385 void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
121
|
386 MachineBasicBlock::iterator MI, unsigned DestReg,
|
|
|
387 int FrameIndex, const TargetRegisterClass *RC,
|
|
77
|
388 const TargetRegisterInfo *TRI) const override;
|
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
389
|
|
77
|
390 void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
|
|
391 SmallVectorImpl<MachineOperand> &Addr,
|
|
|
392 const TargetRegisterClass *RC,
|
|
|
393 MachineInstr::mmo_iterator MMOBegin,
|
|
|
394 MachineInstr::mmo_iterator MMOEnd,
|
|
121
|
395 SmallVectorImpl<MachineInstr *> &NewMIs) const;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
396
|
|
120
|
397 bool expandPostRAPseudo(MachineInstr &MI) const override;
|
|
|
398
|
|
|
399 /// Check whether the target can fold a load that feeds a subreg operand
|
|
|
400 /// (or a subreg operand that feeds a store).
|
|
|
401 bool isSubregFoldable() const override { return true; }
|
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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changeset
|
402
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
403 /// foldMemoryOperand - If this target supports it, fold a load or store of
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
404 /// the specified stack slot into the specified machine instruction for the
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
405 /// specified operand(s). If this is possible, the target should perform the
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
406 /// folding and return true, otherwise it should return false. If it folds
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
407 /// the instruction, it is likely that the MachineInstruction the iterator
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
408 /// references has been changed.
|
|
120
|
409 MachineInstr *
|
|
|
410 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
|
|
|
411 ArrayRef<unsigned> Ops,
|
|
|
412 MachineBasicBlock::iterator InsertPt, int FrameIndex,
|
|
|
413 LiveIntervals *LIS = nullptr) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
414
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
415 /// foldMemoryOperand - Same as the previous version except it allows folding
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
416 /// of any load and store from / to any address, not just from a specific
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
417 /// stack slot.
|
|
120
|
418 MachineInstr *foldMemoryOperandImpl(
|
|
|
419 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
|
|
|
420 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
|
|
|
421 LiveIntervals *LIS = nullptr) const override;
|
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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diff
changeset
|
422
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
423 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
424 /// a store or a load and a store into two or more instruction. If this is
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
425 /// possible, returns true as well as the new instructions by reference.
|
|
120
|
426 bool
|
|
|
427 unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg,
|
|
|
428 bool UnfoldLoad, bool UnfoldStore,
|
|
|
429 SmallVectorImpl<MachineInstr *> &NewMIs) const override;
|
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
430
|
|
77
|
431 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
|
|
121
|
432 SmallVectorImpl<SDNode *> &NewNodes) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
433
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
434 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
435 /// instruction after load / store are unfolded from an instruction of the
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
436 /// specified opcode. It returns zero if the specified unfolding is not
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
437 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
438 /// index of the operand which will hold the register holding the loaded
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
439 /// value.
|
|
121
|
440 unsigned
|
|
|
441 getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
|
|
|
442 unsigned *LoadRegIndex = nullptr) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
443
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
444 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
445 /// to determine if two loads are loading from the same base address. It
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
446 /// should only return true if the base pointers are the same and the
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
447 /// only differences between the two addresses are the offset. It also returns
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
448 /// the offsets by reference.
|
|
77
|
449 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
|
|
|
450 int64_t &Offset2) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
451
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
452 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
|
|
121
|
453 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
|
|
|
454 /// should be scheduled togther. On some targets if two loads are loading from
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455 /// addresses in the same cache line, it's better if they are scheduled
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456 /// together. This function takes two integers that represent the load offsets
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457 /// from the common base address. It returns true if it decides it's desirable
|
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458 /// to schedule the two loads together. "NumLoads" is the number of loads that
|
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459 /// have already been scheduled after Load1.
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121
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460 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1,
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|
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461 int64_t Offset2,
|
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77
|
462 unsigned NumLoads) const override;
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463
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121
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464 void getNoop(MCInst &NopInst) const override;
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465
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77
|
466 bool
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120
|
467 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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468
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469 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
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470 /// instruction that defines the specified register class.
|
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77
|
471 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
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|
|
472
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|
|
473 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha
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474 /// would clobber the EFLAGS condition register. Note the result may be
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|
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475 /// conservative. If it cannot definitely determine the safety after visiting
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476 /// a few instructions in each direction it assumes it's not safe.
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|
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477 bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
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|
|
478 MachineBasicBlock::iterator I) const;
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479
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|
95
|
480 /// True if MI has a condition code def, e.g. EFLAGS, that is
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|
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481 /// not marked dead.
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120
|
482 bool hasLiveCondCodeDef(MachineInstr &MI) const;
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95
|
483
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484 /// getGlobalBaseReg - Return a virtual register initialized with the
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485 /// the global base register value. Output instructions required to
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486 /// initialize the register in the function entry block, if necessary.
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487 ///
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488 unsigned getGlobalBaseReg(MachineFunction *MF) const;
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489
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490 std::pair<uint16_t, uint16_t>
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120
|
491 getExecutionDomain(const MachineInstr &MI) const override;
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492
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120
|
493 void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
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494
|
|
77
|
495 unsigned
|
|
120
|
496 getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
|
|
|
497 const TargetRegisterInfo *TRI) const override;
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|
|
498 unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
|
|
77
|
499 const TargetRegisterInfo *TRI) const override;
|
|
120
|
500 void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
|
|
77
|
501 const TargetRegisterInfo *TRI) const override;
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502
|
|
120
|
503 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
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504 unsigned OpNum,
|
|
95
|
505 ArrayRef<MachineOperand> MOs,
|
|
|
506 MachineBasicBlock::iterator InsertPt,
|
|
83
|
507 unsigned Size, unsigned Alignment,
|
|
|
508 bool AllowCommute) const;
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509
|
|
77
|
510 bool isHighLatencyDef(int opc) const override;
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511
|
|
95
|
512 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
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513 const MachineRegisterInfo *MRI,
|
|
120
|
514 const MachineInstr &DefMI, unsigned DefIdx,
|
|
|
515 const MachineInstr &UseMI,
|
|
77
|
516 unsigned UseIdx) const override;
|
|
120
|
517
|
|
121
|
518 bool useMachineCombiner() const override { return true; }
|
|
95
|
519
|
|
|
520 bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
|
|
|
521
|
|
|
522 bool hasReassociableOperands(const MachineInstr &Inst,
|
|
|
523 const MachineBasicBlock *MBB) const override;
|
|
|
524
|
|
|
525 void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
|
|
|
526 MachineInstr &NewMI1,
|
|
|
527 MachineInstr &NewMI2) const override;
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528
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529 /// analyzeCompare - For a comparison instruction, return the source registers
|
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530 /// in SrcReg and SrcReg2 if having two register operands, and the value it
|
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|
531 /// compares against in CmpValue. Return true if the comparison instruction
|
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532 /// can be analyzed.
|
|
120
|
533 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
|
|
77
|
534 unsigned &SrcReg2, int &CmpMask,
|
|
|
535 int &CmpValue) const override;
|
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|
536
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|
537 /// optimizeCompareInstr - Check if there exists an earlier instruction that
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
538 /// operates on the same source operands and sets flags in the same way as
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
539 /// Compare; remove Compare if possible.
|
|
120
|
540 bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
|
|
77
|
541 unsigned SrcReg2, int CmpMask, int CmpValue,
|
|
|
542 const MachineRegisterInfo *MRI) const override;
|
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|
543
|
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diff
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|
544 /// optimizeLoadInstr - Try to remove the load by folding it to a register
|
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|
545 /// operand at the use. We fold the load instructions if and only if the
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
546 /// def and use are in the same BB. We only look at one load and see
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
547 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
|
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|
548 /// defined by the load we are trying to fold. DefMI returns the machine
|
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diff
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|
549 /// instruction that defines FoldAsLoadDefReg, and the function returns
|
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|
550 /// the machine instruction generated due to folding.
|
|
120
|
551 MachineInstr *optimizeLoadInstr(MachineInstr &MI,
|
|
77
|
552 const MachineRegisterInfo *MRI,
|
|
|
553 unsigned &FoldAsLoadDefReg,
|
|
|
554 MachineInstr *&DefMI) const override;
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|
555
|
|
95
|
556 std::pair<unsigned, unsigned>
|
|
|
557 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
|
|
|
558
|
|
|
559 ArrayRef<std::pair<unsigned, const char *>>
|
|
|
560 getSerializableDirectMachineOperandTargetFlags() const override;
|
|
|
561
|
|
121
|
562 virtual MachineOutlinerInfo getOutlininingCandidateInfo(
|
|
|
563 std::vector<
|
|
|
564 std::pair<MachineBasicBlock::iterator, MachineBasicBlock::iterator>>
|
|
|
565 &RepeatedSequenceLocs) const override;
|
|
|
566
|
|
|
567 bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
|
|
|
568 bool OutlineFromLinkOnceODRs) const override;
|
|
|
569
|
|
|
570 llvm::X86GenInstrInfo::MachineOutlinerInstrType
|
|
|
571 getOutliningType(MachineInstr &MI) const override;
|
|
|
572
|
|
|
573 void insertOutlinerEpilogue(MachineBasicBlock &MBB, MachineFunction &MF,
|
|
|
574 const MachineOutlinerInfo &MInfo) const override;
|
|
|
575
|
|
|
576 void insertOutlinerPrologue(MachineBasicBlock &MBB, MachineFunction &MF,
|
|
|
577 const MachineOutlinerInfo &MInfo) const override;
|
|
|
578
|
|
|
579 MachineBasicBlock::iterator
|
|
|
580 insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
|
|
|
581 MachineBasicBlock::iterator &It, MachineFunction &MF,
|
|
|
582 const MachineOutlinerInfo &MInfo) const override;
|
|
120
|
583
|
|
95
|
584 protected:
|
|
|
585 /// Commutes the operands in the given instruction by changing the operands
|
|
|
586 /// order and/or changing the instruction's opcode and/or the immediate value
|
|
|
587 /// operand.
|
|
|
588 ///
|
|
|
589 /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands
|
|
|
590 /// to be commuted.
|
|
|
591 ///
|
|
|
592 /// Do not call this method for a non-commutable instruction or
|
|
|
593 /// non-commutable operands.
|
|
|
594 /// Even though the instruction is commutable, the method may still
|
|
|
595 /// fail to commute the operands, null pointer is returned in such cases.
|
|
120
|
596 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
|
|
95
|
597 unsigned CommuteOpIdx1,
|
|
|
598 unsigned CommuteOpIdx2) const override;
|
|
|
599
|
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|
600 private:
|
|
120
|
601 MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc,
|
|
|
602 MachineFunction::iterator &MFI,
|
|
|
603 MachineInstr &MI,
|
|
|
604 LiveVariables *LV) const;
|
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
605
|
|
100
|
606 /// Handles memory folding for special case instructions, for instance those
|
|
|
607 /// requiring custom manipulation of the address.
|
|
120
|
608 MachineInstr *foldMemoryOperandCustom(MachineFunction &MF, MachineInstr &MI,
|
|
100
|
609 unsigned OpNum,
|
|
|
610 ArrayRef<MachineOperand> MOs,
|
|
|
611 MachineBasicBlock::iterator InsertPt,
|
|
|
612 unsigned Size, unsigned Align) const;
|
|
|
613
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
614 /// isFrameOperand - Return true and the FrameIndex if the specified
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
615 /// operand and follow operands form a reference to the stack frame.
|
|
120
|
616 bool isFrameOperand(const MachineInstr &MI, unsigned int Op,
|
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
617 int &FrameIndex) const;
|
|
120
|
618
|
|
|
619 /// Returns true iff the routine could find two commutable operands in the
|
|
|
620 /// given machine instruction with 3 vector inputs.
|
|
|
621 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
|
|
|
622 /// input values can be re-defined in this method only if the input values
|
|
|
623 /// are not pre-defined, which is designated by the special value
|
|
|
624 /// 'CommuteAnyOperandIndex' assigned to it.
|
|
|
625 /// If both of indices are pre-defined and refer to some operands, then the
|
|
|
626 /// method simply returns true if the corresponding operands are commutable
|
|
|
627 /// and returns false otherwise.
|
|
|
628 ///
|
|
|
629 /// For example, calling this method this way:
|
|
|
630 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
|
|
|
631 /// findThreeSrcCommutedOpIndices(MI, Op1, Op2);
|
|
|
632 /// can be interpreted as a query asking to find an operand that would be
|
|
|
633 /// commutable with the operand#1.
|
|
|
634 bool findThreeSrcCommutedOpIndices(const MachineInstr &MI,
|
|
|
635 unsigned &SrcOpIdx1,
|
|
|
636 unsigned &SrcOpIdx2) const;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
637 };
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
638
|
|
121
|
639 } // namespace llvm
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
640
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
641 #endif
|
