0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
3 // The LLVM Compiler Infrastructure
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
4 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
5 // This file is distributed under the University of Illinois Open Source
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
6 // License. See LICENSE.TXT for details.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
7 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
8 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
9 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
10 // This file contains the X86 implementation of the TargetInstrInfo class.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
11 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
12 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
13
|
|
77
|
14 #ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H
|
|
|
15 #define LLVM_LIB_TARGET_X86_X86INSTRINFO_H
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
16
|
|
77
|
17 #include "MCTargetDesc/X86BaseInfo.h"
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
18 #include "X86RegisterInfo.h"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
19 #include "llvm/ADT/DenseMap.h"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
20 #include "llvm/Target/TargetInstrInfo.h"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
21
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
22 #define GET_INSTRINFO_HEADER
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
23 #include "X86GenInstrInfo.inc"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
24
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
25 namespace llvm {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
26 class X86RegisterInfo;
|
|
77
|
27 class X86Subtarget;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
28
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
29 namespace X86 {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
30 // X86 specific condition code. These correspond to X86_*_COND in
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
31 // X86InstrInfo.td. They must be kept in synch.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
32 enum CondCode {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
33 COND_A = 0,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
34 COND_AE = 1,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
35 COND_B = 2,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
36 COND_BE = 3,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
37 COND_E = 4,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
38 COND_G = 5,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
39 COND_GE = 6,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
40 COND_L = 7,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
41 COND_LE = 8,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
42 COND_NE = 9,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
43 COND_NO = 10,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
44 COND_NP = 11,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
45 COND_NS = 12,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
46 COND_O = 13,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
47 COND_P = 14,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
48 COND_S = 15,
|
|
77
|
49 LAST_VALID_COND = COND_S,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
50
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
51 // Artificial condition codes. These are used by AnalyzeBranch
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
52 // to indicate a block terminated with two conditional branches to
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
53 // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
54 // which can't be represented on x86 with a single condition. These
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
55 // are never used in MachineInstrs.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
56 COND_NE_OR_P,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
57 COND_NP_OR_E,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
58
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
59 COND_INVALID
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
60 };
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
61
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
62 // Turn condition code into conditional branch opcode.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
63 unsigned GetCondBranchFromCond(CondCode CC);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
64
|
|
77
|
65 /// \brief Return a set opcode for the given condition and whether it has
|
|
|
66 /// a memory operand.
|
|
|
67 unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand = false);
|
|
|
68
|
|
|
69 /// \brief Return a cmov opcode for the given condition, register size in
|
|
|
70 /// bytes, and operand type.
|
|
|
71 unsigned getCMovFromCond(CondCode CC, unsigned RegBytes,
|
|
|
72 bool HasMemoryOperand = false);
|
|
|
73
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
74 // Turn CMov opcode into condition code.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
75 CondCode getCondFromCMovOpc(unsigned Opc);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
76
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
77 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
78 /// e.g. turning COND_E to COND_NE.
|
|
77
|
79 CondCode GetOppositeBranchCondition(CondCode CC);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
80 } // end namespace X86;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
81
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
82
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
83 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
84 /// a reference to a stub for a global, not the global itself.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
85 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
86 switch (TargetFlag) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
87 case X86II::MO_DLLIMPORT: // dllimport stub.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
88 case X86II::MO_GOTPCREL: // rip-relative GOT reference.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
89 case X86II::MO_GOT: // normal GOT reference.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
90 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
91 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
92 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
93 return true;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
94 default:
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
95 return false;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
96 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
97 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
98
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
99 /// isGlobalRelativeToPICBase - Return true if the specified global value
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
100 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
101 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
102 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
103 switch (TargetFlag) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
104 case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
105 case X86II::MO_GOT: // isPICStyleGOT: other global.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
106 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
107 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
108 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
109 case X86II::MO_TLVP: // ??? Pretty sure..
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
110 return true;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
111 default:
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
112 return false;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
113 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
114 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
115
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
116 inline static bool isScale(const MachineOperand &MO) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
117 return MO.isImm() &&
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
118 (MO.getImm() == 1 || MO.getImm() == 2 ||
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
119 MO.getImm() == 4 || MO.getImm() == 8);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
120 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
121
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
122 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
123 if (MI->getOperand(Op).isFI()) return true;
|
|
77
|
124 return Op+X86::AddrSegmentReg <= MI->getNumOperands() &&
|
|
|
125 MI->getOperand(Op+X86::AddrBaseReg).isReg() &&
|
|
|
126 isScale(MI->getOperand(Op+X86::AddrScaleAmt)) &&
|
|
|
127 MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
|
|
|
128 (MI->getOperand(Op+X86::AddrDisp).isImm() ||
|
|
|
129 MI->getOperand(Op+X86::AddrDisp).isGlobal() ||
|
|
|
130 MI->getOperand(Op+X86::AddrDisp).isCPI() ||
|
|
|
131 MI->getOperand(Op+X86::AddrDisp).isJTI());
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
132 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
133
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
134 inline static bool isMem(const MachineInstr *MI, unsigned Op) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
135 if (MI->getOperand(Op).isFI()) return true;
|
|
77
|
136 return Op+X86::AddrNumOperands <= MI->getNumOperands() &&
|
|
|
137 MI->getOperand(Op+X86::AddrSegmentReg).isReg() &&
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
138 isLeaMem(MI, Op);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
139 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
140
|
|
77
|
141 class X86InstrInfo final : public X86GenInstrInfo {
|
|
|
142 X86Subtarget &Subtarget;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
143 const X86RegisterInfo RI;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
144
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
145 /// RegOp2MemOpTable3Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
146 /// RegOp2MemOpTable2, RegOp2MemOpTable3 - Load / store folding opcode maps.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
147 ///
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
148 typedef DenseMap<unsigned,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
149 std::pair<unsigned, unsigned> > RegOp2MemOpTableType;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
150 RegOp2MemOpTableType RegOp2MemOpTable2Addr;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
151 RegOp2MemOpTableType RegOp2MemOpTable0;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
152 RegOp2MemOpTableType RegOp2MemOpTable1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
153 RegOp2MemOpTableType RegOp2MemOpTable2;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
154 RegOp2MemOpTableType RegOp2MemOpTable3;
|
|
83
|
155 RegOp2MemOpTableType RegOp2MemOpTable4;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
156
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
157 /// MemOp2RegOpTable - Load / store unfolding opcode map.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
158 ///
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
159 typedef DenseMap<unsigned,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
160 std::pair<unsigned, unsigned> > MemOp2RegOpTableType;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
161 MemOp2RegOpTableType MemOp2RegOpTable;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
162
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
163 static void AddTableEntry(RegOp2MemOpTableType &R2MTable,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
164 MemOp2RegOpTableType &M2RTable,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
165 unsigned RegOp, unsigned MemOp, unsigned Flags);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
166
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
167 virtual void anchor();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
168
|
|
95
|
169 bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
|
|
|
170 MachineBasicBlock *&FBB,
|
|
|
171 SmallVectorImpl<MachineOperand> &Cond,
|
|
|
172 SmallVectorImpl<MachineInstr *> &CondBranches,
|
|
|
173 bool AllowModify) const;
|
|
|
174
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
175 public:
|
|
77
|
176 explicit X86InstrInfo(X86Subtarget &STI);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
177
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
178 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
179 /// such, whenever a client has an instance of instruction info, it should
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
180 /// always be able to get register info as well (through this method).
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
181 ///
|
|
77
|
182 const X86RegisterInfo &getRegisterInfo() const { return RI; }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
183
|
|
83
|
184 /// getSPAdjust - This returns the stack pointer adjustment made by
|
|
|
185 /// this instruction. For x86, we need to handle more complex call
|
|
|
186 /// sequences involving PUSHes.
|
|
|
187 int getSPAdjust(const MachineInstr *MI) const override;
|
|
|
188
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
189 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
190 /// extension instruction. That is, it's like a copy where it's legal for the
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
191 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
192 /// true, then it's expected the pre-extension value is available as a subreg
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
193 /// of the result register. This also returns the sub-register index in
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
194 /// SubIdx.
|
|
77
|
195 bool isCoalescableExtInstr(const MachineInstr &MI,
|
|
|
196 unsigned &SrcReg, unsigned &DstReg,
|
|
|
197 unsigned &SubIdx) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
198
|
|
77
|
199 unsigned isLoadFromStackSlot(const MachineInstr *MI,
|
|
|
200 int &FrameIndex) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
201 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
202 /// stack locations as well. This uses a heuristic so it isn't
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
203 /// reliable for correctness.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
204 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
|
|
77
|
205 int &FrameIndex) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
206
|
|
77
|
207 unsigned isStoreToStackSlot(const MachineInstr *MI,
|
|
|
208 int &FrameIndex) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
209 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
210 /// stack locations as well. This uses a heuristic so it isn't
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
211 /// reliable for correctness.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
212 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
|
|
77
|
213 int &FrameIndex) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
214
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
215 bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
|
|
77
|
216 AliasAnalysis *AA) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
217 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
218 unsigned DestReg, unsigned SubIdx,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
219 const MachineInstr *Orig,
|
|
77
|
220 const TargetRegisterInfo &TRI) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
221
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
222 /// Given an operand within a MachineInstr, insert preceding code to put it
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
223 /// into the right format for a particular kind of LEA instruction. This may
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
224 /// involve using an appropriate super-register instead (with an implicit use
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
225 /// of the original) or creating a new virtual register and inserting COPY
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
226 /// instructions to get the data into the right class.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
227 ///
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
228 /// Reference parameters are set to indicate how caller should add this
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
229 /// operand to the LEA instruction.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
230 bool classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
231 unsigned LEAOpcode, bool AllowSP,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
232 unsigned &NewSrc, bool &isKill,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
233 bool &isUndef, MachineOperand &ImplicitOp) const;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
234
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
235 /// convertToThreeAddress - This method must be implemented by targets that
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
236 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
237 /// may be able to convert a two-address instruction into a true
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
238 /// three-address instruction on demand. This allows the X86 target (for
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
239 /// example) to convert ADD and SHL instructions into LEA instructions if they
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
240 /// would require register copies due to two-addressness.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
241 ///
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
242 /// This method returns a null pointer if the transformation cannot be
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
243 /// performed, otherwise it returns the new instruction.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
244 ///
|
|
77
|
245 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
|
|
|
246 MachineBasicBlock::iterator &MBBI,
|
|
|
247 LiveVariables *LV) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
248
|
|
95
|
249 /// Returns true iff the routine could find two commutable operands in the
|
|
|
250 /// given machine instruction.
|
|
|
251 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
|
|
|
252 /// input values can be re-defined in this method only if the input values
|
|
|
253 /// are not pre-defined, which is designated by the special value
|
|
|
254 /// 'CommuteAnyOperandIndex' assigned to it.
|
|
|
255 /// If both of indices are pre-defined and refer to some operands, then the
|
|
|
256 /// method simply returns true if the corresponding operands are commutable
|
|
|
257 /// and returns false otherwise.
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
258 ///
|
|
95
|
259 /// For example, calling this method this way:
|
|
|
260 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
|
|
|
261 /// findCommutedOpIndices(MI, Op1, Op2);
|
|
|
262 /// can be interpreted as a query asking to find an operand that would be
|
|
|
263 /// commutable with the operand#1.
|
|
77
|
264 bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
|
|
|
265 unsigned &SrcOpIdx2) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
266
|
|
100
|
267 /// Returns true if the routine could find two commutable operands
|
|
|
268 /// in the given FMA instruction. Otherwise, returns false.
|
|
|
269 ///
|
|
|
270 /// \p SrcOpIdx1 and \p SrcOpIdx2 are INPUT and OUTPUT arguments.
|
|
|
271 /// The output indices of the commuted operands are returned in these
|
|
|
272 /// arguments. Also, the input values of these arguments may be preset either
|
|
|
273 /// to indices of operands that must be commuted or be equal to a special
|
|
|
274 /// value 'CommuteAnyOperandIndex' which means that the corresponding
|
|
|
275 /// operand index is not set and this method is free to pick any of
|
|
|
276 /// available commutable operands.
|
|
|
277 ///
|
|
|
278 /// For example, calling this method this way:
|
|
|
279 /// unsigned Idx1 = 1, Idx2 = CommuteAnyOperandIndex;
|
|
|
280 /// findFMA3CommutedOpIndices(MI, Idx1, Idx2);
|
|
|
281 /// can be interpreted as a query asking if the operand #1 can be swapped
|
|
|
282 /// with any other available operand (e.g. operand #2, operand #3, etc.).
|
|
|
283 ///
|
|
|
284 /// The returned FMA opcode may differ from the opcode in the given MI.
|
|
|
285 /// For example, commuting the operands #1 and #3 in the following FMA
|
|
|
286 /// FMA213 #1, #2, #3
|
|
|
287 /// results into instruction with adjusted opcode:
|
|
|
288 /// FMA231 #3, #2, #1
|
|
|
289 bool findFMA3CommutedOpIndices(MachineInstr *MI,
|
|
|
290 unsigned &SrcOpIdx1,
|
|
|
291 unsigned &SrcOpIdx2) const;
|
|
|
292
|
|
|
293 /// Returns an adjusted FMA opcode that must be used in FMA instruction that
|
|
|
294 /// performs the same computations as the given MI but which has the operands
|
|
|
295 /// \p SrcOpIdx1 and \p SrcOpIdx2 commuted.
|
|
|
296 /// It may return 0 if it is unsafe to commute the operands.
|
|
|
297 ///
|
|
|
298 /// The returned FMA opcode may differ from the opcode in the given \p MI.
|
|
|
299 /// For example, commuting the operands #1 and #3 in the following FMA
|
|
|
300 /// FMA213 #1, #2, #3
|
|
|
301 /// results into instruction with adjusted opcode:
|
|
|
302 /// FMA231 #3, #2, #1
|
|
|
303 unsigned getFMA3OpcodeToCommuteOperands(MachineInstr *MI,
|
|
|
304 unsigned SrcOpIdx1,
|
|
|
305 unsigned SrcOpIdx2) const;
|
|
|
306
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
307 // Branch analysis.
|
|
77
|
308 bool isUnpredicatedTerminator(const MachineInstr* MI) const override;
|
|
|
309 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
|
|
|
310 MachineBasicBlock *&FBB,
|
|
|
311 SmallVectorImpl<MachineOperand> &Cond,
|
|
|
312 bool AllowModify) const override;
|
|
95
|
313
|
|
|
314 bool getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
|
|
|
315 unsigned &Offset,
|
|
|
316 const TargetRegisterInfo *TRI) const override;
|
|
|
317 bool AnalyzeBranchPredicate(MachineBasicBlock &MBB,
|
|
|
318 TargetInstrInfo::MachineBranchPredicate &MBP,
|
|
|
319 bool AllowModify = false) const override;
|
|
|
320
|
|
77
|
321 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
|
|
|
322 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
|
95
|
323 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
|
|
77
|
324 DebugLoc DL) const override;
|
|
95
|
325 bool canInsertSelect(const MachineBasicBlock&, ArrayRef<MachineOperand> Cond,
|
|
77
|
326 unsigned, unsigned, int&, int&, int&) const override;
|
|
|
327 void insertSelect(MachineBasicBlock &MBB,
|
|
|
328 MachineBasicBlock::iterator MI, DebugLoc DL,
|
|
95
|
329 unsigned DstReg, ArrayRef<MachineOperand> Cond,
|
|
77
|
330 unsigned TrueReg, unsigned FalseReg) const override;
|
|
|
331 void copyPhysReg(MachineBasicBlock &MBB,
|
|
|
332 MachineBasicBlock::iterator MI, DebugLoc DL,
|
|
|
333 unsigned DestReg, unsigned SrcReg,
|
|
|
334 bool KillSrc) const override;
|
|
|
335 void storeRegToStackSlot(MachineBasicBlock &MBB,
|
|
|
336 MachineBasicBlock::iterator MI,
|
|
|
337 unsigned SrcReg, bool isKill, int FrameIndex,
|
|
|
338 const TargetRegisterClass *RC,
|
|
|
339 const TargetRegisterInfo *TRI) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
340
|
|
77
|
341 void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
|
|
|
342 SmallVectorImpl<MachineOperand> &Addr,
|
|
|
343 const TargetRegisterClass *RC,
|
|
|
344 MachineInstr::mmo_iterator MMOBegin,
|
|
|
345 MachineInstr::mmo_iterator MMOEnd,
|
|
|
346 SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
347
|
|
77
|
348 void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
|
349 MachineBasicBlock::iterator MI,
|
|
|
350 unsigned DestReg, int FrameIndex,
|
|
|
351 const TargetRegisterClass *RC,
|
|
|
352 const TargetRegisterInfo *TRI) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
353
|
|
77
|
354 void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
|
|
355 SmallVectorImpl<MachineOperand> &Addr,
|
|
|
356 const TargetRegisterClass *RC,
|
|
|
357 MachineInstr::mmo_iterator MMOBegin,
|
|
|
358 MachineInstr::mmo_iterator MMOEnd,
|
|
|
359 SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
360
|
|
77
|
361 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
362
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
363 /// foldMemoryOperand - If this target supports it, fold a load or store of
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
364 /// the specified stack slot into the specified machine instruction for the
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
365 /// specified operand(s). If this is possible, the target should perform the
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
366 /// folding and return true, otherwise it should return false. If it folds
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
367 /// the instruction, it is likely that the MachineInstruction the iterator
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
368 /// references has been changed.
|
|
95
|
369 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
|
|
|
370 ArrayRef<unsigned> Ops,
|
|
|
371 MachineBasicBlock::iterator InsertPt,
|
|
77
|
372 int FrameIndex) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
373
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
374 /// foldMemoryOperand - Same as the previous version except it allows folding
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
375 /// of any load and store from / to any address, not just from a specific
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
376 /// stack slot.
|
|
95
|
377 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
|
|
|
378 ArrayRef<unsigned> Ops,
|
|
|
379 MachineBasicBlock::iterator InsertPt,
|
|
|
380 MachineInstr *LoadMI) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
381
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
382 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
383 /// a store or a load and a store into two or more instruction. If this is
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
384 /// possible, returns true as well as the new instructions by reference.
|
|
77
|
385 bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
|
|
|
386 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
|
|
|
387 SmallVectorImpl<MachineInstr*> &NewMIs) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
388
|
|
77
|
389 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
|
|
|
390 SmallVectorImpl<SDNode*> &NewNodes) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
391
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
392 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
393 /// instruction after load / store are unfolded from an instruction of the
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
394 /// specified opcode. It returns zero if the specified unfolding is not
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
395 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
396 /// index of the operand which will hold the register holding the loaded
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
397 /// value.
|
|
77
|
398 unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
|
|
|
399 bool UnfoldLoad, bool UnfoldStore,
|
|
|
400 unsigned *LoadRegIndex = nullptr) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
401
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
402 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
403 /// to determine if two loads are loading from the same base address. It
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
404 /// should only return true if the base pointers are the same and the
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
405 /// only differences between the two addresses are the offset. It also returns
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
406 /// the offsets by reference.
|
|
77
|
407 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
|
|
|
408 int64_t &Offset2) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
409
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
410 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
411 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
412 /// be scheduled togther. On some targets if two loads are loading from
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
413 /// addresses in the same cache line, it's better if they are scheduled
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
414 /// together. This function takes two integers that represent the load offsets
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
415 /// from the common base address. It returns true if it decides it's desirable
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
416 /// to schedule the two loads together. "NumLoads" is the number of loads that
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
417 /// have already been scheduled after Load1.
|
|
77
|
418 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
|
|
|
419 int64_t Offset1, int64_t Offset2,
|
|
|
420 unsigned NumLoads) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
421
|
|
77
|
422 bool shouldScheduleAdjacent(MachineInstr* First,
|
|
|
423 MachineInstr *Second) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
424
|
|
77
|
425 void getNoopForMachoTarget(MCInst &NopInst) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
426
|
|
77
|
427 bool
|
|
|
428 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
429
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
430 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
431 /// instruction that defines the specified register class.
|
|
77
|
432 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
|
|
|
433
|
|
|
434 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha
|
|
|
435 /// would clobber the EFLAGS condition register. Note the result may be
|
|
|
436 /// conservative. If it cannot definitely determine the safety after visiting
|
|
|
437 /// a few instructions in each direction it assumes it's not safe.
|
|
|
438 bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
|
|
|
439 MachineBasicBlock::iterator I) const;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
440
|
|
95
|
441 /// True if MI has a condition code def, e.g. EFLAGS, that is
|
|
|
442 /// not marked dead.
|
|
|
443 bool hasLiveCondCodeDef(MachineInstr *MI) const;
|
|
|
444
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
445 /// getGlobalBaseReg - Return a virtual register initialized with the
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
446 /// the global base register value. Output instructions required to
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
447 /// initialize the register in the function entry block, if necessary.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
448 ///
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
449 unsigned getGlobalBaseReg(MachineFunction *MF) const;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
450
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
451 std::pair<uint16_t, uint16_t>
|
|
77
|
452 getExecutionDomain(const MachineInstr *MI) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
453
|
|
77
|
454 void setExecutionDomain(MachineInstr *MI, unsigned Domain) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
455
|
|
77
|
456 unsigned
|
|
|
457 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
|
|
|
458 const TargetRegisterInfo *TRI) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
459 unsigned getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
|
|
77
|
460 const TargetRegisterInfo *TRI) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
461 void breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
|
|
77
|
462 const TargetRegisterInfo *TRI) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
463
|
|
95
|
464 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
465 unsigned OpNum,
|
|
95
|
466 ArrayRef<MachineOperand> MOs,
|
|
|
467 MachineBasicBlock::iterator InsertPt,
|
|
83
|
468 unsigned Size, unsigned Alignment,
|
|
|
469 bool AllowCommute) const;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
470
|
|
77
|
471 void
|
|
|
472 getUnconditionalBranch(MCInst &Branch,
|
|
|
473 const MCSymbolRefExpr *BranchTarget) const override;
|
|
|
474
|
|
|
475 void getTrap(MCInst &MI) const override;
|
|
|
476
|
|
83
|
477 unsigned getJumpInstrTableEntryBound() const override;
|
|
|
478
|
|
77
|
479 bool isHighLatencyDef(int opc) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
480
|
|
95
|
481 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
482 const MachineRegisterInfo *MRI,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
483 const MachineInstr *DefMI, unsigned DefIdx,
|
|
77
|
484 const MachineInstr *UseMI,
|
|
|
485 unsigned UseIdx) const override;
|
|
95
|
486
|
|
|
487 bool useMachineCombiner() const override {
|
|
|
488 return true;
|
|
|
489 }
|
|
|
490
|
|
|
491 bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
|
|
|
492
|
|
|
493 bool hasReassociableOperands(const MachineInstr &Inst,
|
|
|
494 const MachineBasicBlock *MBB) const override;
|
|
|
495
|
|
|
496 void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
|
|
|
497 MachineInstr &NewMI1,
|
|
|
498 MachineInstr &NewMI2) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
499
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
500 /// analyzeCompare - For a comparison instruction, return the source registers
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
501 /// in SrcReg and SrcReg2 if having two register operands, and the value it
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
502 /// compares against in CmpValue. Return true if the comparison instruction
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
503 /// can be analyzed.
|
|
77
|
504 bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
|
|
|
505 unsigned &SrcReg2, int &CmpMask,
|
|
|
506 int &CmpValue) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
507
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
508 /// optimizeCompareInstr - Check if there exists an earlier instruction that
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
509 /// operates on the same source operands and sets flags in the same way as
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
510 /// Compare; remove Compare if possible.
|
|
77
|
511 bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
|
|
|
512 unsigned SrcReg2, int CmpMask, int CmpValue,
|
|
|
513 const MachineRegisterInfo *MRI) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
514
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
515 /// optimizeLoadInstr - Try to remove the load by folding it to a register
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
516 /// operand at the use. We fold the load instructions if and only if the
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
517 /// def and use are in the same BB. We only look at one load and see
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
518 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
519 /// defined by the load we are trying to fold. DefMI returns the machine
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
520 /// instruction that defines FoldAsLoadDefReg, and the function returns
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
521 /// the machine instruction generated due to folding.
|
|
77
|
522 MachineInstr* optimizeLoadInstr(MachineInstr *MI,
|
|
|
523 const MachineRegisterInfo *MRI,
|
|
|
524 unsigned &FoldAsLoadDefReg,
|
|
|
525 MachineInstr *&DefMI) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
526
|
|
95
|
527 std::pair<unsigned, unsigned>
|
|
|
528 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
|
|
|
529
|
|
|
530 ArrayRef<std::pair<unsigned, const char *>>
|
|
|
531 getSerializableDirectMachineOperandTargetFlags() const override;
|
|
|
532
|
|
|
533 protected:
|
|
|
534 /// Commutes the operands in the given instruction by changing the operands
|
|
|
535 /// order and/or changing the instruction's opcode and/or the immediate value
|
|
|
536 /// operand.
|
|
|
537 ///
|
|
|
538 /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands
|
|
|
539 /// to be commuted.
|
|
|
540 ///
|
|
|
541 /// Do not call this method for a non-commutable instruction or
|
|
|
542 /// non-commutable operands.
|
|
|
543 /// Even though the instruction is commutable, the method may still
|
|
|
544 /// fail to commute the operands, null pointer is returned in such cases.
|
|
|
545 MachineInstr *commuteInstructionImpl(MachineInstr *MI, bool NewMI,
|
|
|
546 unsigned CommuteOpIdx1,
|
|
|
547 unsigned CommuteOpIdx2) const override;
|
|
|
548
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
549 private:
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
550 MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
551 MachineFunction::iterator &MFI,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
552 MachineBasicBlock::iterator &MBBI,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
553 LiveVariables *LV) const;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
554
|
|
100
|
555 /// Handles memory folding for special case instructions, for instance those
|
|
|
556 /// requiring custom manipulation of the address.
|
|
|
557 MachineInstr *foldMemoryOperandCustom(MachineFunction &MF, MachineInstr *MI,
|
|
|
558 unsigned OpNum,
|
|
|
559 ArrayRef<MachineOperand> MOs,
|
|
|
560 MachineBasicBlock::iterator InsertPt,
|
|
|
561 unsigned Size, unsigned Align) const;
|
|
|
562
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
563 /// isFrameOperand - Return true and the FrameIndex if the specified
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
564 /// operand and follow operands form a reference to the stack frame.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
565 bool isFrameOperand(const MachineInstr *MI, unsigned int Op,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
566 int &FrameIndex) const;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
567 };
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
568
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
569 } // End llvm namespace
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
570
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
571 #endif
|
