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LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
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120:1172e4bd9c6f 121:803732b1fca8
1 //===- X86InstrVecCompiler.td - Vector Compiler Patterns ---*- tablegen -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file describes the various vector pseudo instructions used by the
11 // compiler, as well as Pat patterns used during instruction selection.
12 //
13 //===----------------------------------------------------------------------===//
14
15 //===----------------------------------------------------------------------===//
16 // No op bitconverts
17 //===----------------------------------------------------------------------===//
18
19 // Bitcasts between 128-bit vector types. Return the original type since
20 // no instruction is needed for the conversion
21 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
22 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
23 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
24 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
25 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
27 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
28 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
29 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
30 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
33 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
34 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
35 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
38 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
39 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
40 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
41 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
42 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
43 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
44 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
45 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
46 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
48 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
49 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
50 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
51 def : Pat<(f128 (bitconvert (i128 FR128:$src))), (f128 FR128:$src)>;
52 def : Pat<(i128 (bitconvert (f128 FR128:$src))), (i128 FR128:$src)>;
53
54 // Bitcasts between 256-bit vector types. Return the original type since
55 // no instruction is needed for the conversion
56 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
57 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
58 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
59 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
60 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
61 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
62 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
63 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
64 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
65 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
66 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
67 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
68 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
69 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
70 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
71 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
72 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
73 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
74 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
75 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
76 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
77 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
78 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
79 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
80 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
81 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
82 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
83 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
84 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
85 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
86
87 // Bitcasts between 512-bit vector types. Return the original type since
88 // no instruction is needed for the conversion.
89 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
90 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
91 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
92 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
93 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
94 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
95 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
96 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
97 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
98 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
99 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
100 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
101 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
102 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
103 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
104 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
105 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
106 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
107 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
108 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
109 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
110 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
111 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
112 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
113 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
114 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
115 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
116 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
117 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
118 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
119 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
120
121
122 //===----------------------------------------------------------------------===//
123 // Non-instruction patterns
124 //===----------------------------------------------------------------------===//
125
126 // A vector extract of the first f32/f64 position is a subregister copy
127 def : Pat<(f32 (extractelt (v4f32 VR128:$src), (iPTR 0))),
128 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
129 def : Pat<(f64 (extractelt (v2f64 VR128:$src), (iPTR 0))),
130 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
131
132 // Implicitly promote a 32-bit scalar to a vector.
133 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
134 (COPY_TO_REGCLASS FR32:$src, VR128)>;
135 // Implicitly promote a 64-bit scalar to a vector.
136 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
137 (COPY_TO_REGCLASS FR64:$src, VR128)>;
138
139
140 //===----------------------------------------------------------------------===//
141 // Subvector tricks
142 //===----------------------------------------------------------------------===//
143
144 // Patterns for insert_subvector/extract_subvector to/from index=0
145 multiclass subvector_subreg_lowering<RegisterClass subRC, ValueType subVT,
146 RegisterClass RC, ValueType VT,
147 SubRegIndex subIdx> {
148 def : Pat<(subVT (extract_subvector (VT RC:$src), (iPTR 0))),
149 (subVT (EXTRACT_SUBREG RC:$src, subIdx))>;
150
151 let AddedComplexity = 25 in // to give priority over vinsertf128rm
152 def : Pat<(VT (insert_subvector undef, subRC:$src, (iPTR 0))),
153 (VT (INSERT_SUBREG (IMPLICIT_DEF), subRC:$src, subIdx))>;
154 }
155
156 // A 128-bit subvector extract from the first 256-bit vector position is a
157 // subregister copy that needs no instruction. Likewise, a 128-bit subvector
158 // insert to the first 256-bit vector position is a subregister copy that needs
159 // no instruction.
160 defm : subvector_subreg_lowering<VR128, v4i32, VR256, v8i32, sub_xmm>;
161 defm : subvector_subreg_lowering<VR128, v4f32, VR256, v8f32, sub_xmm>;
162 defm : subvector_subreg_lowering<VR128, v2i64, VR256, v4i64, sub_xmm>;
163 defm : subvector_subreg_lowering<VR128, v2f64, VR256, v4f64, sub_xmm>;
164 defm : subvector_subreg_lowering<VR128, v8i16, VR256, v16i16, sub_xmm>;
165 defm : subvector_subreg_lowering<VR128, v16i8, VR256, v32i8, sub_xmm>;
166
167 // A 128-bit subvector extract from the first 512-bit vector position is a
168 // subregister copy that needs no instruction. Likewise, a 128-bit subvector
169 // insert to the first 512-bit vector position is a subregister copy that needs
170 // no instruction.
171 defm : subvector_subreg_lowering<VR128, v4i32, VR512, v16i32, sub_xmm>;
172 defm : subvector_subreg_lowering<VR128, v4f32, VR512, v16f32, sub_xmm>;
173 defm : subvector_subreg_lowering<VR128, v2i64, VR512, v8i64, sub_xmm>;
174 defm : subvector_subreg_lowering<VR128, v2f64, VR512, v8f64, sub_xmm>;
175 defm : subvector_subreg_lowering<VR128, v8i16, VR512, v32i16, sub_xmm>;
176 defm : subvector_subreg_lowering<VR128, v16i8, VR512, v64i8, sub_xmm>;
177
178 // A 128-bit subvector extract from the first 512-bit vector position is a
179 // subregister copy that needs no instruction. Likewise, a 128-bit subvector
180 // insert to the first 512-bit vector position is a subregister copy that needs
181 // no instruction.
182 defm : subvector_subreg_lowering<VR256, v8i32, VR512, v16i32, sub_ymm>;
183 defm : subvector_subreg_lowering<VR256, v8f32, VR512, v16f32, sub_ymm>;
184 defm : subvector_subreg_lowering<VR256, v4i64, VR512, v8i64, sub_ymm>;
185 defm : subvector_subreg_lowering<VR256, v4f64, VR512, v8f64, sub_ymm>;
186 defm : subvector_subreg_lowering<VR256, v16i16, VR512, v32i16, sub_ymm>;
187 defm : subvector_subreg_lowering<VR256, v32i8, VR512, v64i8, sub_ymm>;
188
189
190 multiclass subvector_store_lowering<string AlignedStr, string UnalignedStr,
191 RegisterClass RC, ValueType DstTy,
192 ValueType SrcTy, SubRegIndex SubIdx> {
193 def : Pat<(alignedstore (DstTy (extract_subvector
194 (SrcTy RC:$src), (iPTR 0))), addr:$dst),
195 (!cast<Instruction>("VMOV"#AlignedStr#"mr") addr:$dst,
196 (DstTy (EXTRACT_SUBREG RC:$src, SubIdx)))>;
197
198 def : Pat<(store (DstTy (extract_subvector
199 (SrcTy RC:$src), (iPTR 0))), addr:$dst),
200 (!cast<Instruction>("VMOV"#UnalignedStr#"mr") addr:$dst,
201 (DstTy (EXTRACT_SUBREG RC:$src, SubIdx)))>;
202 }
203
204 let Predicates = [HasAVX, NoVLX] in {
205 defm : subvector_store_lowering<"APD", "UPD", VR256X, v2f64, v4f64, sub_xmm>;
206 defm : subvector_store_lowering<"APS", "UPS", VR256X, v4f32, v8f32, sub_xmm>;
207 defm : subvector_store_lowering<"DQA", "DQU", VR256X, v2i64, v4i64, sub_xmm>;
208 defm : subvector_store_lowering<"DQA", "DQU", VR256X, v4i32, v8i32, sub_xmm>;
209 defm : subvector_store_lowering<"DQA", "DQU", VR256X, v8i16, v16i16, sub_xmm>;
210 defm : subvector_store_lowering<"DQA", "DQU", VR256X, v16i8, v32i8, sub_xmm>;
211 }
212
213 let Predicates = [HasVLX] in {
214 // Special patterns for storing subvector extracts of lower 128-bits
215 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
216 defm : subvector_store_lowering<"APDZ128", "UPDZ128", VR256X, v2f64, v4f64,
217 sub_xmm>;
218 defm : subvector_store_lowering<"APSZ128", "UPSZ128", VR256X, v4f32, v8f32,
219 sub_xmm>;
220 defm : subvector_store_lowering<"DQA32Z128", "DQU32Z128", VR256X, v2i64,
221 v4i64, sub_xmm>;
222 defm : subvector_store_lowering<"DQA32Z128", "DQU32Z128", VR256X, v4i32,
223 v8i32, sub_xmm>;
224 defm : subvector_store_lowering<"DQA32Z128", "DQU32Z128", VR256X, v8i16,
225 v16i16, sub_xmm>;
226 defm : subvector_store_lowering<"DQA32Z128", "DQU32Z128", VR256X, v16i8,
227 v32i8, sub_xmm>;
228
229 // Special patterns for storing subvector extracts of lower 128-bits of 512.
230 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
231 defm : subvector_store_lowering<"APDZ128", "UPDZ128", VR512, v2f64, v8f64,
232 sub_xmm>;
233 defm : subvector_store_lowering<"APSZ128", "UPSZ128", VR512, v4f32, v16f32,
234 sub_xmm>;
235 defm : subvector_store_lowering<"DQA32Z128", "DQU32Z128", VR512, v2i64,
236 v8i64, sub_xmm>;
237 defm : subvector_store_lowering<"DQA32Z128", "DQU32Z128", VR512, v4i32,
238 v16i32, sub_xmm>;
239 defm : subvector_store_lowering<"DQA32Z128", "DQU32Z128", VR512, v8i16,
240 v32i16, sub_xmm>;
241 defm : subvector_store_lowering<"DQA32Z128", "DQU32Z128", VR512, v16i8,
242 v64i8, sub_xmm>;
243
244 // Special patterns for storing subvector extracts of lower 256-bits of 512.
245 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
246 defm : subvector_store_lowering<"APDZ256", "UPDZ256", VR512, v4f64, v8f64,
247 sub_ymm>;
248 defm : subvector_store_lowering<"APSZ256", "UPSZ256", VR512, v8f32, v16f32,
249 sub_ymm>;
250 defm : subvector_store_lowering<"DQA32Z256", "DQU32Z256", VR512, v4i64,
251 v8i64, sub_ymm>;
252 defm : subvector_store_lowering<"DQA32Z256", "DQU32Z256", VR512, v8i32,
253 v16i32, sub_ymm>;
254 defm : subvector_store_lowering<"DQA32Z256", "DQU32Z256", VR512, v16i16,
255 v32i16, sub_ymm>;
256 defm : subvector_store_lowering<"DQA32Z256", "DQU32Z256", VR512, v32i8,
257 v64i8, sub_ymm>;
258 }
259
260 // If we're inserting into an all zeros vector, just use a plain move which
261 // will zero the upper bits.
262 // TODO: Is there a safe way to detect whether the producing instruction
263 // already zeroed the upper bits?
264 multiclass subvector_zero_lowering<string MoveStr, RegisterClass RC,
265 ValueType DstTy, ValueType SrcTy,
266 ValueType ZeroTy, PatFrag memop,
267 SubRegIndex SubIdx> {
268 def : Pat<(DstTy (insert_subvector (bitconvert (ZeroTy immAllZerosV)),
269 (SrcTy RC:$src), (iPTR 0))),
270 (SUBREG_TO_REG (i64 0),
271 (!cast<Instruction>("VMOV"#MoveStr#"rr") RC:$src), SubIdx)>;
272
273 def : Pat<(DstTy (insert_subvector (bitconvert (ZeroTy immAllZerosV)),
274 (SrcTy (bitconvert (memop addr:$src))),
275 (iPTR 0))),
276 (SUBREG_TO_REG (i64 0),
277 (!cast<Instruction>("VMOV"#MoveStr#"rm") addr:$src), SubIdx)>;
278 }
279
280 let Predicates = [HasAVX, NoVLX] in {
281 defm : subvector_zero_lowering<"APD", VR128, v4f64, v2f64, v8i32, loadv2f64,
282 sub_xmm>;
283 defm : subvector_zero_lowering<"APS", VR128, v8f32, v4f32, v8i32, loadv4f32,
284 sub_xmm>;
285 defm : subvector_zero_lowering<"DQA", VR128, v4i64, v2i64, v8i32, loadv2i64,
286 sub_xmm>;
287 defm : subvector_zero_lowering<"DQA", VR128, v8i32, v4i32, v8i32, loadv2i64,
288 sub_xmm>;
289 defm : subvector_zero_lowering<"DQA", VR128, v16i16, v8i16, v8i32, loadv2i64,
290 sub_xmm>;
291 defm : subvector_zero_lowering<"DQA", VR128, v32i8, v16i8, v8i32, loadv2i64,
292 sub_xmm>;
293 }
294
295 let Predicates = [HasVLX] in {
296 defm : subvector_zero_lowering<"APDZ128", VR128X, v4f64, v2f64, v8i32,
297 loadv2f64, sub_xmm>;
298 defm : subvector_zero_lowering<"APSZ128", VR128X, v8f32, v4f32, v8i32,
299 loadv4f32, sub_xmm>;
300 defm : subvector_zero_lowering<"DQA64Z128", VR128X, v4i64, v2i64, v8i32,
301 loadv2i64, sub_xmm>;
302 defm : subvector_zero_lowering<"DQA64Z128", VR128X, v8i32, v4i32, v8i32,
303 loadv2i64, sub_xmm>;
304 defm : subvector_zero_lowering<"DQA64Z128", VR128X, v16i16, v8i16, v8i32,
305 loadv2i64, sub_xmm>;
306 defm : subvector_zero_lowering<"DQA64Z128", VR128X, v32i8, v16i8, v8i32,
307 loadv2i64, sub_xmm>;
308
309 defm : subvector_zero_lowering<"APDZ128", VR128X, v8f64, v2f64, v16i32,
310 loadv2f64, sub_xmm>;
311 defm : subvector_zero_lowering<"APSZ128", VR128X, v16f32, v4f32, v16i32,
312 loadv4f32, sub_xmm>;
313 defm : subvector_zero_lowering<"DQA64Z128", VR128X, v8i64, v2i64, v16i32,
314 loadv2i64, sub_xmm>;
315 defm : subvector_zero_lowering<"DQA64Z128", VR128X, v16i32, v4i32, v16i32,
316 loadv2i64, sub_xmm>;
317 defm : subvector_zero_lowering<"DQA64Z128", VR128X, v32i16, v8i16, v16i32,
318 loadv2i64, sub_xmm>;
319 defm : subvector_zero_lowering<"DQA64Z128", VR128X, v64i8, v16i8, v16i32,
320 loadv2i64, sub_xmm>;
321
322 defm : subvector_zero_lowering<"APDZ256", VR256X, v8f64, v4f64, v16i32,
323 loadv4f64, sub_ymm>;
324 defm : subvector_zero_lowering<"APSZ256", VR256X, v16f32, v8f32, v16i32,
325 loadv8f32, sub_ymm>;
326 defm : subvector_zero_lowering<"DQA64Z256", VR256X, v8i64, v4i64, v16i32,
327 loadv4i64, sub_ymm>;
328 defm : subvector_zero_lowering<"DQA64Z256", VR256X, v16i32, v8i32, v16i32,
329 loadv4i64, sub_ymm>;
330 defm : subvector_zero_lowering<"DQA64Z256", VR256X, v32i16, v16i16, v16i32,
331 loadv4i64, sub_ymm>;
332 defm : subvector_zero_lowering<"DQA64Z256", VR256X, v64i8, v32i8, v16i32,
333 loadv4i64, sub_ymm>;
334 }
335
336 let Predicates = [HasAVX512, NoVLX] in {
337 defm : subvector_zero_lowering<"APD", VR128, v8f64, v2f64, v16i32, loadv2f64,
338 sub_xmm>;
339 defm : subvector_zero_lowering<"APS", VR128, v16f32, v4f32, v16i32, loadv4f32,
340 sub_xmm>;
341 defm : subvector_zero_lowering<"DQA", VR128, v8i64, v2i64, v16i32, loadv2i64,
342 sub_xmm>;
343 defm : subvector_zero_lowering<"DQA", VR128, v16i32, v4i32, v16i32, loadv2i64,
344 sub_xmm>;
345 defm : subvector_zero_lowering<"DQA", VR128, v32i16, v8i16, v16i32, loadv2i64,
346 sub_xmm>;
347 defm : subvector_zero_lowering<"DQA", VR128, v64i8, v16i8, v16i32, loadv2i64,
348 sub_xmm>;
349
350 defm : subvector_zero_lowering<"APDY", VR256, v8f64, v4f64, v16i32,
351 loadv4f64, sub_ymm>;
352 defm : subvector_zero_lowering<"APSY", VR256, v16f32, v8f32, v16i32,
353 loadv8f32, sub_ymm>;
354 defm : subvector_zero_lowering<"DQAY", VR256, v8i64, v4i64, v16i32,
355 loadv4i64, sub_ymm>;
356 defm : subvector_zero_lowering<"DQAY", VR256, v16i32, v8i32, v16i32,
357 loadv4i64, sub_ymm>;
358 defm : subvector_zero_lowering<"DQAY", VR256, v32i16, v16i16, v16i32,
359 loadv4i64, sub_ymm>;
360 defm : subvector_zero_lowering<"DQAY", VR256, v64i8, v32i8, v16i32,
361 loadv4i64, sub_ymm>;
362 }
363
364 // List of opcodes that guaranteed to zero the upper elements of vector regs.
365 // TODO: Ideally this would be a blacklist instead of a whitelist. But SHA
366 // intrinsics and some MMX->XMM move instructions that aren't VEX encoded make
367 // this difficult. So starting with a couple opcodes used by reduction loops
368 // where we explicitly insert zeros.
369 class veczeroupper<ValueType vt, RegisterClass RC> :
370 PatLeaf<(vt RC:$src), [{
371 return N->getOpcode() == X86ISD::VPMADDWD ||
372 N->getOpcode() == X86ISD::PSADBW;
373 }]>;
374
375 def zeroupperv2f64 : veczeroupper<v2f64, VR128>;
376 def zeroupperv4f32 : veczeroupper<v4f32, VR128>;
377 def zeroupperv2i64 : veczeroupper<v2i64, VR128>;
378 def zeroupperv4i32 : veczeroupper<v4i32, VR128>;
379 def zeroupperv8i16 : veczeroupper<v8i16, VR128>;
380 def zeroupperv16i8 : veczeroupper<v16i8, VR128>;
381
382 def zeroupperv4f64 : veczeroupper<v4f64, VR256>;
383 def zeroupperv8f32 : veczeroupper<v8f32, VR256>;
384 def zeroupperv4i64 : veczeroupper<v4i64, VR256>;
385 def zeroupperv8i32 : veczeroupper<v8i32, VR256>;
386 def zeroupperv16i16 : veczeroupper<v16i16, VR256>;
387 def zeroupperv32i8 : veczeroupper<v32i8, VR256>;
388
389
390 // If we can guarantee the upper elements have already been zeroed we can elide
391 // an explicit zeroing.
392 multiclass subvector_zero_ellision<RegisterClass RC, ValueType DstTy,
393 ValueType SrcTy, ValueType ZeroTy,
394 SubRegIndex SubIdx, PatLeaf Zeroupper> {
395 def : Pat<(DstTy (insert_subvector (bitconvert (ZeroTy immAllZerosV)),
396 Zeroupper:$src, (iPTR 0))),
397 (SUBREG_TO_REG (i64 0), RC:$src, SubIdx)>;
398 }
399
400 // 128->256
401 defm: subvector_zero_ellision<VR128, v4f64, v2f64, v8i32, sub_xmm, zeroupperv2f64>;
402 defm: subvector_zero_ellision<VR128, v8f32, v4f32, v8i32, sub_xmm, zeroupperv4f32>;
403 defm: subvector_zero_ellision<VR128, v4i64, v2i64, v8i32, sub_xmm, zeroupperv2i64>;
404 defm: subvector_zero_ellision<VR128, v8i32, v4i32, v8i32, sub_xmm, zeroupperv4i32>;
405 defm: subvector_zero_ellision<VR128, v16i16, v8i16, v8i32, sub_xmm, zeroupperv8i16>;
406 defm: subvector_zero_ellision<VR128, v32i8, v16i8, v8i32, sub_xmm, zeroupperv16i8>;
407
408 // 128->512
409 defm: subvector_zero_ellision<VR128, v8f64, v2f64, v16i32, sub_xmm, zeroupperv2f64>;
410 defm: subvector_zero_ellision<VR128, v16f32, v4f32, v16i32, sub_xmm, zeroupperv4f32>;
411 defm: subvector_zero_ellision<VR128, v8i64, v2i64, v16i32, sub_xmm, zeroupperv2i64>;
412 defm: subvector_zero_ellision<VR128, v16i32, v4i32, v16i32, sub_xmm, zeroupperv4i32>;
413 defm: subvector_zero_ellision<VR128, v32i16, v8i16, v16i32, sub_xmm, zeroupperv8i16>;
414 defm: subvector_zero_ellision<VR128, v64i8, v16i8, v16i32, sub_xmm, zeroupperv16i8>;
415
416 // 256->512
417 defm: subvector_zero_ellision<VR256, v8f64, v4f64, v16i32, sub_ymm, zeroupperv4f64>;
418 defm: subvector_zero_ellision<VR256, v16f32, v8f32, v16i32, sub_ymm, zeroupperv8f32>;
419 defm: subvector_zero_ellision<VR256, v8i64, v4i64, v16i32, sub_ymm, zeroupperv4i64>;
420 defm: subvector_zero_ellision<VR256, v16i32, v8i32, v16i32, sub_ymm, zeroupperv8i32>;
421 defm: subvector_zero_ellision<VR256, v32i16, v16i16, v16i32, sub_ymm, zeroupperv16i16>;
422 defm: subvector_zero_ellision<VR256, v64i8, v32i8, v16i32, sub_ymm, zeroupperv32i8>;
423
424
425 class maskzeroupper<ValueType vt, RegisterClass RC> :
426 PatLeaf<(vt RC:$src), [{
427 return isMaskZeroExtended(N);
428 }]>;
429
430 def maskzeroupperv2i1 : maskzeroupper<v2i1, VK2>;
431 def maskzeroupperv4i1 : maskzeroupper<v4i1, VK4>;
432 def maskzeroupperv8i1 : maskzeroupper<v8i1, VK8>;
433 def maskzeroupperv16i1 : maskzeroupper<v16i1, VK16>;
434 def maskzeroupperv32i1 : maskzeroupper<v32i1, VK32>;
435
436 // The patterns determine if we can depend on the upper bits of a mask register
437 // being zeroed by the previous operation so that we can skip explicit
438 // zeroing.
439 let Predicates = [HasBWI] in {
440 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
441 maskzeroupperv8i1:$src, (iPTR 0))),
442 (COPY_TO_REGCLASS VK8:$src, VK32)>;
443 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
444 maskzeroupperv16i1:$src, (iPTR 0))),
445 (COPY_TO_REGCLASS VK16:$src, VK32)>;
446 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
447 maskzeroupperv8i1:$src, (iPTR 0))),
448 (COPY_TO_REGCLASS VK8:$src, VK64)>;
449 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
450 maskzeroupperv16i1:$src, (iPTR 0))),
451 (COPY_TO_REGCLASS VK16:$src, VK64)>;
452 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
453 maskzeroupperv32i1:$src, (iPTR 0))),
454 (COPY_TO_REGCLASS VK32:$src, VK64)>;
455 }
456
457 let Predicates = [HasAVX512] in {
458 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
459 maskzeroupperv8i1:$src, (iPTR 0))),
460 (COPY_TO_REGCLASS VK8:$src, VK16)>;
461 }
462
463 let Predicates = [HasVLX] in {
464 def : Pat<(v4i1 (insert_subvector (v4i1 immAllZerosV),
465 maskzeroupperv2i1:$src, (iPTR 0))),
466 (COPY_TO_REGCLASS VK2:$src, VK4)>;
467 def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV),
468 maskzeroupperv2i1:$src, (iPTR 0))),
469 (COPY_TO_REGCLASS VK2:$src, VK8)>;
470 def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV),
471 maskzeroupperv4i1:$src, (iPTR 0))),
472 (COPY_TO_REGCLASS VK4:$src, VK8)>;
473 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
474 maskzeroupperv2i1:$src, (iPTR 0))),
475 (COPY_TO_REGCLASS VK2:$src, VK16)>;
476 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
477 maskzeroupperv4i1:$src, (iPTR 0))),
478 (COPY_TO_REGCLASS VK4:$src, VK16)>;
479 }
480
481 let Predicates = [HasBWI, HasVLX] in {
482 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
483 maskzeroupperv2i1:$src, (iPTR 0))),
484 (COPY_TO_REGCLASS VK2:$src, VK32)>;
485 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
486 maskzeroupperv4i1:$src, (iPTR 0))),
487 (COPY_TO_REGCLASS VK4:$src, VK32)>;
488 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
489 maskzeroupperv2i1:$src, (iPTR 0))),
490 (COPY_TO_REGCLASS VK2:$src, VK64)>;
491 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
492 maskzeroupperv4i1:$src, (iPTR 0))),
493 (COPY_TO_REGCLASS VK4:$src, VK64)>;
494 }
495
496 // If the bits are not zero we have to fall back to explicitly zeroing by
497 // using shifts.
498 let Predicates = [HasAVX512, NoVLX] in {
499 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
500 (v8i1 VK8:$mask), (iPTR 0))),
501 (KSHIFTRWri (KSHIFTLWri (COPY_TO_REGCLASS VK8:$mask, VK16),
502 (i8 8)), (i8 8))>;
503 }