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annotate lib/Target/Sparc/SparcISelLowering.h @ 134:3a76565eade5 LLVM5.0.1

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update 5.0.1
author mir3636
date Sat, 17 Feb 2018 09:57:20 +0900
parents 803732b1fca8
children c2174574ed3a
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1 //===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file defines the interfaces that Sparc uses to lower LLVM code into a
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11 // selection DAG.
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12 //
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13 //===----------------------------------------------------------------------===//
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15 #ifndef LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
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16 #define LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
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17
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18 #include "Sparc.h"
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19 #include "llvm/CodeGen/TargetLowering.h"
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20
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21 namespace llvm {
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22 class SparcSubtarget;
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23
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24 namespace SPISD {
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25 enum NodeType : unsigned {
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26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
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27 CMPICC, // Compare two GPR operands, set icc+xcc.
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28 CMPFCC, // Compare two FP operands, set fcc.
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29 BRICC, // Branch to dest on icc condition
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30 BRXCC, // Branch to dest on xcc condition (64-bit only).
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31 BRFCC, // Branch to dest on fcc condition
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32 SELECT_ICC, // Select between two values using the current ICC flags.
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33 SELECT_XCC, // Select between two values using the current XCC flags.
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34 SELECT_FCC, // Select between two values using the current FCC flags.
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35
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36 EH_SJLJ_SETJMP, // builtin setjmp operation
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37 EH_SJLJ_LONGJMP, // builtin longjmp operation
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38
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39 Hi, Lo, // Hi/Lo operations, typically on a global address.
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40
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41 FTOI, // FP to Int within a FP register.
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42 ITOF, // Int to FP within a FP register.
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43 FTOX, // FP to Int64 within a FP register.
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44 XTOF, // Int64 to FP within a FP register.
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45
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46 CALL, // A call instruction.
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47 RET_FLAG, // Return with a flag operand.
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48 GLOBAL_BASE_REG, // Global base reg for PIC.
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49 FLUSHW, // FLUSH register windows to stack.
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50
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51 TLS_ADD, // For Thread Local Storage (TLS).
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52 TLS_LD,
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53 TLS_CALL
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54 };
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55 }
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56
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57 class SparcTargetLowering : public TargetLowering {
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58 const SparcSubtarget *Subtarget;
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59 public:
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60 SparcTargetLowering(const TargetMachine &TM, const SparcSubtarget &STI);
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61 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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62
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63 bool useSoftFloat() const override;
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64
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65 /// computeKnownBitsForTargetNode - Determine which of the bits specified
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66 /// in Mask are known to be either zero or one and return them in the
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67 /// KnownZero/KnownOne bitsets.
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68 void computeKnownBitsForTargetNode(const SDValue Op,
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69 KnownBits &Known,
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70 const APInt &DemandedElts,
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71 const SelectionDAG &DAG,
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72 unsigned Depth = 0) const override;
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73
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74 MachineBasicBlock *
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75 EmitInstrWithCustomInserter(MachineInstr &MI,
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76 MachineBasicBlock *MBB) const override;
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78 const char *getTargetNodeName(unsigned Opcode) const override;
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80 ConstraintType getConstraintType(StringRef Constraint) const override;
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81 ConstraintWeight
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82 getSingleConstraintMatchWeight(AsmOperandInfo &info,
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83 const char *constraint) const override;
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84 void LowerAsmOperandForConstraint(SDValue Op,
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85 std::string &Constraint,
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86 std::vector<SDValue> &Ops,
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87 SelectionDAG &DAG) const override;
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88
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89 unsigned
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90 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
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91 if (ConstraintCode == "o")
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92 return InlineAsm::Constraint_o;
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93 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
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94 }
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96 std::pair<unsigned, const TargetRegisterClass *>
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97 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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98 StringRef Constraint, MVT VT) const override;
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99
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100 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
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101 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
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102 return MVT::i32;
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103 }
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104
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105 unsigned getRegisterByName(const char* RegName, EVT VT,
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106 SelectionDAG &DAG) const override;
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107
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108 /// If a physical register, this returns the register that receives the
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109 /// exception address on entry to an EH pad.
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110 unsigned
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111 getExceptionPointerRegister(const Constant *PersonalityFn) const override {
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112 return SP::I0;
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113 }
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114
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115 /// If a physical register, this returns the register that receives the
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116 /// exception typeid on entry to a landing pad.
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117 unsigned
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118 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
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119 return SP::I1;
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120 }
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121
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122 /// Override to support customized stack guard loading.
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123 bool useLoadStackGuardNode() const override;
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124 void insertSSPDeclarations(Module &M) const override;
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125
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126 /// getSetCCResultType - Return the ISD::SETCC ValueType
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127 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
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128 EVT VT) const override;
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129
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130 SDValue
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131 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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132 const SmallVectorImpl<ISD::InputArg> &Ins,
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133 const SDLoc &dl, SelectionDAG &DAG,
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134 SmallVectorImpl<SDValue> &InVals) const override;
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135 SDValue LowerFormalArguments_32(SDValue Chain, CallingConv::ID CallConv,
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136 bool isVarArg,
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137 const SmallVectorImpl<ISD::InputArg> &Ins,
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138 const SDLoc &dl, SelectionDAG &DAG,
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139 SmallVectorImpl<SDValue> &InVals) const;
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140 SDValue LowerFormalArguments_64(SDValue Chain, CallingConv::ID CallConv,
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141 bool isVarArg,
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142 const SmallVectorImpl<ISD::InputArg> &Ins,
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143 const SDLoc &dl, SelectionDAG &DAG,
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144 SmallVectorImpl<SDValue> &InVals) const;
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145
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146 SDValue
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147 LowerCall(TargetLowering::CallLoweringInfo &CLI,
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148 SmallVectorImpl<SDValue> &InVals) const override;
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149 SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
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150 SmallVectorImpl<SDValue> &InVals) const;
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151 SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
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152 SmallVectorImpl<SDValue> &InVals) const;
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153
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154 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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155 const SmallVectorImpl<ISD::OutputArg> &Outs,
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156 const SmallVectorImpl<SDValue> &OutVals,
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157 const SDLoc &dl, SelectionDAG &DAG) const override;
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158 SDValue LowerReturn_32(SDValue Chain, CallingConv::ID CallConv,
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159 bool IsVarArg,
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160 const SmallVectorImpl<ISD::OutputArg> &Outs,
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161 const SmallVectorImpl<SDValue> &OutVals,
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162 const SDLoc &DL, SelectionDAG &DAG) const;
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163 SDValue LowerReturn_64(SDValue Chain, CallingConv::ID CallConv,
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164 bool IsVarArg,
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165 const SmallVectorImpl<ISD::OutputArg> &Outs,
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166 const SmallVectorImpl<SDValue> &OutVals,
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167 const SDLoc &DL, SelectionDAG &DAG) const;
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168
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169 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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170 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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171 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
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172 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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173
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174 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG,
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175 const SparcTargetLowering &TLI) const ;
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176 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG,
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177 const SparcTargetLowering &TLI) const ;
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178
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179 unsigned getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const;
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180 SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;
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181 SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
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182 SelectionDAG &DAG) const;
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183 SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const;
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184
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185 SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, SDValue Arg,
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186 const SDLoc &DL, SelectionDAG &DAG) const;
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187 SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG,
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188 const char *LibFuncName,
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189 unsigned numArgs) const;
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190 SDValue LowerF128Compare(SDValue LHS, SDValue RHS, unsigned &SPCC,
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191 const SDLoc &DL, SelectionDAG &DAG) const;
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192
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193 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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194
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195 bool ShouldShrinkFPConstant(EVT VT) const override {
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196 // Do not shrink FP constpool if VT == MVT::f128.
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197 // (ldd, call _Q_fdtoq) is more expensive than two ldds.
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198 return VT != MVT::f128;
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199 }
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200
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201 bool shouldInsertFencesForAtomic(const Instruction *I) const override {
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202 // FIXME: We insert fences for each atomics and generate
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203 // sub-optimal code for PSO/TSO. (Approximately nobody uses any
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204 // mode but TSO, which makes this even more silly)
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205 return true;
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206 }
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207
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208 AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
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209
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210 void ReplaceNodeResults(SDNode *N,
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211 SmallVectorImpl<SDValue>& Results,
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212 SelectionDAG &DAG) const override;
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213
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214 MachineBasicBlock *expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB,
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215 unsigned BROpcode) const;
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216 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI,
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217 MachineBasicBlock *MBB) const;
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218 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI,
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219 MachineBasicBlock *MBB) const;
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220 };
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221 } // end namespace llvm
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222
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223 #endif // SPARC_ISELLOWERING_H