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annotate lib/Target/Mips/MipsSubtarget.cpp @ 83:60c9769439b8 LLVM3.7

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LLVM 3.7
author Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
date Wed, 18 Feb 2015 14:55:36 +0900
parents 54457678186b
children afa8332a0e37
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1 //===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file implements the Mips specific subclass of TargetSubtargetInfo.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 #include "MipsMachineFunction.h"
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15 #include "Mips.h"
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16 #include "MipsRegisterInfo.h"
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17 #include "MipsSubtarget.h"
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18 #include "MipsTargetMachine.h"
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19 #include "llvm/IR/Attributes.h"
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20 #include "llvm/IR/Function.h"
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21 #include "llvm/Support/CommandLine.h"
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22 #include "llvm/Support/Debug.h"
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23 #include "llvm/Support/TargetRegistry.h"
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24 #include "llvm/Support/raw_ostream.h"
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25
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26 using namespace llvm;
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27
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28 #define DEBUG_TYPE "mips-subtarget"
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29
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30 #define GET_SUBTARGETINFO_TARGET_DESC
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31 #define GET_SUBTARGETINFO_CTOR
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32 #include "MipsGenSubtargetInfo.inc"
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33
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34 // FIXME: Maybe this should be on by default when Mips16 is specified
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35 //
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36 static cl::opt<bool> Mixed16_32(
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37 "mips-mixed-16-32",
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38 cl::init(false),
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39 cl::desc("Allow for a mixture of Mips16 "
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40 "and Mips32 code in a single source file"),
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41 cl::Hidden);
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42
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43 static cl::opt<bool> Mips_Os16(
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44 "mips-os16",
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45 cl::init(false),
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46 cl::desc("Compile all functions that don' use "
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47 "floating point as Mips 16"),
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48 cl::Hidden);
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49
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50 static cl::opt<bool>
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51 Mips16HardFloat("mips16-hard-float", cl::NotHidden,
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52 cl::desc("MIPS: mips16 hard float enable."),
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53 cl::init(false));
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54
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55 static cl::opt<bool>
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56 Mips16ConstantIslands(
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57 "mips16-constant-islands", cl::NotHidden,
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58 cl::desc("MIPS: mips16 constant islands enable."),
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59 cl::init(true));
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60
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61 static cl::opt<bool>
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62 GPOpt("mgpopt", cl::Hidden,
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63 cl::desc("MIPS: Enable gp-relative addressing of small data items"));
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64
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65 void MipsSubtarget::anchor() { }
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66
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67 MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
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68 const std::string &FS, bool little,
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69 const MipsTargetMachine &TM)
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70 : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
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71 IsLittle(little), IsSingleFloat(false), IsFPXX(false), NoABICalls(false),
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72 IsFP64bit(false), UseOddSPReg(true), IsNaN2008bit(false),
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73 IsGP64bit(false), HasVFPU(false), HasCnMips(false), HasMips3_32(false),
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74 HasMips3_32r2(false), HasMips4_32(false), HasMips4_32r2(false),
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75 HasMips5_32r2(false), InMips16Mode(false),
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76 InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
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77 HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
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78 HasMSA(false), TM(TM), TargetTriple(TT), TSInfo(*TM.getDataLayout()),
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79 InstrInfo(
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80 MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
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81 FrameLowering(MipsFrameLowering::create(*this)),
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82 TLInfo(MipsTargetLowering::create(TM, *this)) {
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83
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84 PreviousInMips16Mode = InMips16Mode;
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85
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86 if (MipsArchVersion == MipsDefault)
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87 MipsArchVersion = Mips32;
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88
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89 // Don't even attempt to generate code for MIPS-I and MIPS-V. They have not
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90 // been tested and currently exist for the integrated assembler only.
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91 if (MipsArchVersion == Mips1)
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92 report_fatal_error("Code generation for MIPS-I is not implemented", false);
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93 if (MipsArchVersion == Mips5)
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94 report_fatal_error("Code generation for MIPS-V is not implemented", false);
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95
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96 // Check if Architecture and ABI are compatible.
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97 assert(((!isGP64bit() && (isABI_O32() || isABI_EABI())) ||
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98 (isGP64bit() && (isABI_N32() || isABI_N64()))) &&
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99 "Invalid Arch & ABI pair.");
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100
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101 if (hasMSA() && !isFP64bit())
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102 report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). "
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103 "See -mattr=+fp64.",
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104 false);
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105
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106 if (!isABI_O32() && !useOddSPReg())
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107 report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false);
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108
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109 if (IsFPXX && (isABI_N32() || isABI_N64()))
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110 report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false);
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111
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112 if (hasMips32r6()) {
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113 StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
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114
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115 assert(isFP64bit());
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116 assert(isNaN2008());
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117 if (hasDSP())
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118 report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
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119 }
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120
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121 if (NoABICalls && TM.getRelocationModel() == Reloc::PIC_)
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122 report_fatal_error("position-independent code requires '-mabicalls'");
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123
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124 // Set UseSmallSection.
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125 UseSmallSection = GPOpt;
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126 if (!NoABICalls && GPOpt) {
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127 errs() << "warning: cannot use small-data accesses for '-mabicalls'"
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128 << "\n";
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129 UseSmallSection = false;
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130 }
0
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131 }
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132
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133 /// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
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134 bool MipsSubtarget::enablePostMachineScheduler() const { return true; }
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135
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136 void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
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137 CriticalPathRCs.clear();
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138 CriticalPathRCs.push_back(isGP64bit() ?
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139 &Mips::GPR64RegClass : &Mips::GPR32RegClass);
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140 }
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141
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142 CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
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143 return CodeGenOpt::Aggressive;
0
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144 }
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145
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146 MipsSubtarget &
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147 MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
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148 const TargetMachine &TM) {
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149 std::string CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU);
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150
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151 // Parse features string.
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152 ParseSubtargetFeatures(CPUName, FS);
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153 // Initialize scheduling itinerary for the specified CPU.
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154 InstrItins = getInstrItineraryForCPU(CPUName);
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155
83
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156 if (InMips16Mode && !TM.Options.UseSoftFloat)
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157 InMips16HardFloat = true;
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158
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159 return *this;
0
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160 }
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161
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162 bool MipsSubtarget::abiUsesSoftFloat() const {
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163 return TM.Options.UseSoftFloat && !InMips16HardFloat;
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164 }
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165
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166 bool MipsSubtarget::useConstantIslands() {
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167 DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands << "\n");
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168 return Mips16ConstantIslands;
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169 }
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170
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171 Reloc::Model MipsSubtarget::getRelocationModel() const {
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172 return TM.getRelocationModel();
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173 }
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174
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175 bool MipsSubtarget::isABI_EABI() const { return getABI().IsEABI(); }
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176 bool MipsSubtarget::isABI_N64() const { return getABI().IsN64(); }
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177 bool MipsSubtarget::isABI_N32() const { return getABI().IsN32(); }
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178 bool MipsSubtarget::isABI_O32() const { return getABI().IsO32(); }
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179 const MipsABIInfo &MipsSubtarget::getABI() const { return TM.getABI(); }