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annotate lib/Target/Sparc/SparcISelLowering.h @ 148:63bd29f05246

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merged
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Wed, 14 Aug 2019 19:46:37 +0900
parents c2174574ed3a
children
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1 //===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===//
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2 //
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3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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4 // See https://llvm.org/LICENSE.txt for license information.
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5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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6 //
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7 //===----------------------------------------------------------------------===//
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8 //
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9 // This file defines the interfaces that Sparc uses to lower LLVM code into a
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10 // selection DAG.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 #ifndef LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
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15 #define LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
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16
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17 #include "Sparc.h"
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18 #include "llvm/CodeGen/TargetLowering.h"
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19
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20 namespace llvm {
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21 class SparcSubtarget;
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22
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23 namespace SPISD {
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24 enum NodeType : unsigned {
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25 FIRST_NUMBER = ISD::BUILTIN_OP_END,
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26 CMPICC, // Compare two GPR operands, set icc+xcc.
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27 CMPFCC, // Compare two FP operands, set fcc.
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28 BRICC, // Branch to dest on icc condition
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29 BRXCC, // Branch to dest on xcc condition (64-bit only).
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30 BRFCC, // Branch to dest on fcc condition
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31 SELECT_ICC, // Select between two values using the current ICC flags.
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32 SELECT_XCC, // Select between two values using the current XCC flags.
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33 SELECT_FCC, // Select between two values using the current FCC flags.
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34
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35 Hi, Lo, // Hi/Lo operations, typically on a global address.
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36
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37 FTOI, // FP to Int within a FP register.
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38 ITOF, // Int to FP within a FP register.
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39 FTOX, // FP to Int64 within a FP register.
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40 XTOF, // Int64 to FP within a FP register.
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41
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42 CALL, // A call instruction.
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43 RET_FLAG, // Return with a flag operand.
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44 GLOBAL_BASE_REG, // Global base reg for PIC.
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45 FLUSHW, // FLUSH register windows to stack.
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46
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47 TLS_ADD, // For Thread Local Storage (TLS).
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48 TLS_LD,
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49 TLS_CALL
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50 };
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51 }
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53 class SparcTargetLowering : public TargetLowering {
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54 const SparcSubtarget *Subtarget;
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55 public:
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56 SparcTargetLowering(const TargetMachine &TM, const SparcSubtarget &STI);
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57 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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58
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59 bool useSoftFloat() const override;
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60
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61 /// computeKnownBitsForTargetNode - Determine which of the bits specified
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62 /// in Mask are known to be either zero or one and return them in the
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63 /// KnownZero/KnownOne bitsets.
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64 void computeKnownBitsForTargetNode(const SDValue Op,
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65 KnownBits &Known,
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66 const APInt &DemandedElts,
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67 const SelectionDAG &DAG,
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68 unsigned Depth = 0) const override;
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69
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70 MachineBasicBlock *
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71 EmitInstrWithCustomInserter(MachineInstr &MI,
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72 MachineBasicBlock *MBB) const override;
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73
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74 const char *getTargetNodeName(unsigned Opcode) const override;
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76 ConstraintType getConstraintType(StringRef Constraint) const override;
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77 ConstraintWeight
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78 getSingleConstraintMatchWeight(AsmOperandInfo &info,
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79 const char *constraint) const override;
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80 void LowerAsmOperandForConstraint(SDValue Op,
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81 std::string &Constraint,
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82 std::vector<SDValue> &Ops,
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83 SelectionDAG &DAG) const override;
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84
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85 unsigned
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86 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
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87 if (ConstraintCode == "o")
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88 return InlineAsm::Constraint_o;
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89 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
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90 }
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92 std::pair<unsigned, const TargetRegisterClass *>
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93 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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94 StringRef Constraint, MVT VT) const override;
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96 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
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97 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
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98 return MVT::i32;
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99 }
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101 unsigned getRegisterByName(const char* RegName, EVT VT,
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102 SelectionDAG &DAG) const override;
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103
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104 /// If a physical register, this returns the register that receives the
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105 /// exception address on entry to an EH pad.
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106 unsigned
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107 getExceptionPointerRegister(const Constant *PersonalityFn) const override {
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108 return SP::I0;
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109 }
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110
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111 /// If a physical register, this returns the register that receives the
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112 /// exception typeid on entry to a landing pad.
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113 unsigned
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114 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
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115 return SP::I1;
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116 }
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117
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118 /// Override to support customized stack guard loading.
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119 bool useLoadStackGuardNode() const override;
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120 void insertSSPDeclarations(Module &M) const override;
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121
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122 /// getSetCCResultType - Return the ISD::SETCC ValueType
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123 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
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124 EVT VT) const override;
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125
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126 SDValue
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127 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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128 const SmallVectorImpl<ISD::InputArg> &Ins,
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129 const SDLoc &dl, SelectionDAG &DAG,
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130 SmallVectorImpl<SDValue> &InVals) const override;
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131 SDValue LowerFormalArguments_32(SDValue Chain, CallingConv::ID CallConv,
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132 bool isVarArg,
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133 const SmallVectorImpl<ISD::InputArg> &Ins,
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134 const SDLoc &dl, SelectionDAG &DAG,
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135 SmallVectorImpl<SDValue> &InVals) const;
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136 SDValue LowerFormalArguments_64(SDValue Chain, CallingConv::ID CallConv,
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137 bool isVarArg,
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138 const SmallVectorImpl<ISD::InputArg> &Ins,
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139 const SDLoc &dl, SelectionDAG &DAG,
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140 SmallVectorImpl<SDValue> &InVals) const;
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141
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142 SDValue
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143 LowerCall(TargetLowering::CallLoweringInfo &CLI,
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144 SmallVectorImpl<SDValue> &InVals) const override;
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145 SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
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146 SmallVectorImpl<SDValue> &InVals) const;
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147 SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
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148 SmallVectorImpl<SDValue> &InVals) const;
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149
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150 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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151 const SmallVectorImpl<ISD::OutputArg> &Outs,
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152 const SmallVectorImpl<SDValue> &OutVals,
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153 const SDLoc &dl, SelectionDAG &DAG) const override;
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154 SDValue LowerReturn_32(SDValue Chain, CallingConv::ID CallConv,
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155 bool IsVarArg,
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156 const SmallVectorImpl<ISD::OutputArg> &Outs,
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157 const SmallVectorImpl<SDValue> &OutVals,
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158 const SDLoc &DL, SelectionDAG &DAG) const;
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159 SDValue LowerReturn_64(SDValue Chain, CallingConv::ID CallConv,
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160 bool IsVarArg,
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161 const SmallVectorImpl<ISD::OutputArg> &Outs,
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162 const SmallVectorImpl<SDValue> &OutVals,
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163 const SDLoc &DL, SelectionDAG &DAG) const;
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164
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165 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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166 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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167 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
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168 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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169
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170 SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;
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171 SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
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172 SelectionDAG &DAG) const;
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173 SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const;
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174
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175 SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, SDValue Arg,
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176 const SDLoc &DL, SelectionDAG &DAG) const;
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177 SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG,
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178 const char *LibFuncName,
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179 unsigned numArgs) const;
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180 SDValue LowerF128Compare(SDValue LHS, SDValue RHS, unsigned &SPCC,
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181 const SDLoc &DL, SelectionDAG &DAG) const;
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182
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183 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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184
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185 SDValue PerformBITCASTCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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186
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187 SDValue bitcastConstantFPToInt(ConstantFPSDNode *C, const SDLoc &DL,
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188 SelectionDAG &DAG) const;
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189
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190 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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191
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192 bool ShouldShrinkFPConstant(EVT VT) const override {
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193 // Do not shrink FP constpool if VT == MVT::f128.
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194 // (ldd, call _Q_fdtoq) is more expensive than two ldds.
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195 return VT != MVT::f128;
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196 }
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197
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198 bool shouldInsertFencesForAtomic(const Instruction *I) const override {
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199 // FIXME: We insert fences for each atomics and generate
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200 // sub-optimal code for PSO/TSO. (Approximately nobody uses any
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201 // mode but TSO, which makes this even more silly)
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202 return true;
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203 }
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204
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205 AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
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206
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207 void ReplaceNodeResults(SDNode *N,
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208 SmallVectorImpl<SDValue>& Results,
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209 SelectionDAG &DAG) const override;
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210
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211 MachineBasicBlock *expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB,
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212 unsigned BROpcode) const;
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213 };
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214 } // end namespace llvm
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215
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216 #endif // SPARC_ISELLOWERING_H