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1 //===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 // This is the top level entry point for the Mips target.
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10 //===----------------------------------------------------------------------===//
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11
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12 //===----------------------------------------------------------------------===//
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13 // Target-independent interfaces
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14 //===----------------------------------------------------------------------===//
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15
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16 include "llvm/Target/Target.td"
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17
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77
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18 // The overall idea of the PredicateControl class is to chop the Predicates list
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19 // into subsets that are usually overridden independently. This allows
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20 // subclasses to partially override the predicates of their superclasses without
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21 // having to re-add all the existing predicates.
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22 class PredicateControl {
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23 // Predicates for the encoding scheme in use such as HasStdEnc
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24 list<Predicate> EncodingPredicates = [];
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25 // Predicates for the GPR size such as IsGP64bit
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26 list<Predicate> GPRPredicates = [];
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120
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27 // Predicates for the PTR size such as IsPTR64bit
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28 list<Predicate> PTRPredicates = [];
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77
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29 // Predicates for the FGR size and layout such as IsFP64bit
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30 list<Predicate> FGRPredicates = [];
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31 // Predicates for the instruction group membership such as ISA's and ASE's
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32 list<Predicate> InsnPredicates = [];
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95
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33 // Predicate for marking the instruction as usable in hard-float mode only.
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34 list<Predicate> HardFloatPredicate = [];
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77
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35 // Predicates for anything else
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36 list<Predicate> AdditionalPredicates = [];
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37 list<Predicate> Predicates = !listconcat(EncodingPredicates,
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38 GPRPredicates,
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120
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39 PTRPredicates,
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77
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40 FGRPredicates,
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41 InsnPredicates,
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95
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42 HardFloatPredicate,
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77
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43 AdditionalPredicates);
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44 }
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45
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46 // Like Requires<> but for the AdditionalPredicates list
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47 class AdditionalRequires<list<Predicate> preds> {
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48 list<Predicate> AdditionalPredicates = preds;
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49 }
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50
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51 //===----------------------------------------------------------------------===//
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52 // Register File, Calling Conv, Instruction Descriptions
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53 //===----------------------------------------------------------------------===//
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54
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55 include "MipsRegisterInfo.td"
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56 include "MipsSchedule.td"
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57 include "MipsInstrInfo.td"
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58 include "MipsCallingConv.td"
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59
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120
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60 // Avoid forward declaration issues.
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61 include "MipsScheduleP5600.td"
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62 include "MipsScheduleGeneric.td"
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63
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64 def MipsInstrInfo : InstrInfo;
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65
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66 //===----------------------------------------------------------------------===//
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67 // Mips Subtarget features //
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68 //===----------------------------------------------------------------------===//
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69
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77
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70 def FeatureNoABICalls : SubtargetFeature<"noabicalls", "NoABICalls", "true",
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95
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71 "Disable SVR4-style position-independent code">;
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120
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72 def FeaturePTR64Bit : SubtargetFeature<"ptr64", "IsPTR64bit", "true",
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73 "Pointers are 64-bit wide">;
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74 def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
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95
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75 "General Purpose Registers are 64-bit wide">;
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76 def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
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95
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77 "Support 64-bit FP registers">;
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77
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78 def FeatureFPXX : SubtargetFeature<"fpxx", "IsFPXX", "true",
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95
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79 "Support for FPXX">;
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77
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80 def FeatureNaN2008 : SubtargetFeature<"nan2008", "IsNaN2008bit", "true",
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95
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81 "IEEE 754-2008 NaN encoding">;
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82 def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
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83 "true", "Only supports single precision float">;
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95
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84 def FeatureSoftFloat : SubtargetFeature<"soft-float", "IsSoftFloat", "true",
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85 "Does not support floating point instructions">;
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77
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86 def FeatureNoOddSPReg : SubtargetFeature<"nooddspreg", "UseOddSPReg", "false",
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87 "Disable odd numbered single-precision "
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88 "registers">;
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89 def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU",
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95
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90 "true", "Enable vector FPU instructions">;
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77
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91 def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
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92 "Mips I ISA Support [highly experimental]">;
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93 def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
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94 "Mips II ISA Support [highly experimental]",
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95 [FeatureMips1]>;
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96 def FeatureMips3_32 : SubtargetFeature<"mips3_32", "HasMips3_32", "true",
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97 "Subset of MIPS-III that is also in MIPS32 "
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98 "[highly experimental]">;
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99 def FeatureMips3_32r2 : SubtargetFeature<"mips3_32r2", "HasMips3_32r2", "true",
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100 "Subset of MIPS-III that is also in MIPS32r2 "
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101 "[highly experimental]">;
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102 def FeatureMips3 : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3",
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103 "MIPS III ISA Support [highly experimental]",
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104 [FeatureMips2, FeatureMips3_32,
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105 FeatureMips3_32r2, FeatureGP64Bit,
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106 FeatureFP64Bit]>;
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107 def FeatureMips4_32 : SubtargetFeature<"mips4_32", "HasMips4_32", "true",
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108 "Subset of MIPS-IV that is also in MIPS32 "
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109 "[highly experimental]">;
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110 def FeatureMips4_32r2 : SubtargetFeature<"mips4_32r2", "HasMips4_32r2", "true",
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111 "Subset of MIPS-IV that is also in MIPS32r2 "
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112 "[highly experimental]">;
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113 def FeatureMips4 : SubtargetFeature<"mips4", "MipsArchVersion",
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114 "Mips4", "MIPS IV ISA Support",
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115 [FeatureMips3, FeatureMips4_32,
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116 FeatureMips4_32r2]>;
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117 def FeatureMips5_32r2 : SubtargetFeature<"mips5_32r2", "HasMips5_32r2", "true",
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118 "Subset of MIPS-V that is also in MIPS32r2 "
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119 "[highly experimental]">;
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120 def FeatureMips5 : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5",
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121 "MIPS V ISA Support [highly experimental]",
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122 [FeatureMips4, FeatureMips5_32r2]>;
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123 def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
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124 "Mips32 ISA Support",
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125 [FeatureMips2, FeatureMips3_32,
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126 FeatureMips4_32]>;
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127 def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
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128 "Mips32r2", "Mips32r2 ISA Support",
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77
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129 [FeatureMips3_32r2, FeatureMips4_32r2,
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130 FeatureMips5_32r2, FeatureMips32]>;
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131 def FeatureMips32r3 : SubtargetFeature<"mips32r3", "MipsArchVersion",
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132 "Mips32r3", "Mips32r3 ISA Support",
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133 [FeatureMips32r2]>;
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134 def FeatureMips32r5 : SubtargetFeature<"mips32r5", "MipsArchVersion",
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135 "Mips32r5", "Mips32r5 ISA Support",
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136 [FeatureMips32r3]>;
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77
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137 def FeatureMips32r6 : SubtargetFeature<"mips32r6", "MipsArchVersion",
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138 "Mips32r6",
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139 "Mips32r6 ISA Support [experimental]",
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95
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140 [FeatureMips32r5, FeatureFP64Bit,
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141 FeatureNaN2008]>;
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142 def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion",
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143 "Mips64", "Mips64 ISA Support",
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77
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144 [FeatureMips5, FeatureMips32]>;
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145 def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion",
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146 "Mips64r2", "Mips64r2 ISA Support",
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147 [FeatureMips64, FeatureMips32r2]>;
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95
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148 def FeatureMips64r3 : SubtargetFeature<"mips64r3", "MipsArchVersion",
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149 "Mips64r3", "Mips64r3 ISA Support",
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150 [FeatureMips64r2, FeatureMips32r3]>;
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151 def FeatureMips64r5 : SubtargetFeature<"mips64r5", "MipsArchVersion",
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152 "Mips64r5", "Mips64r5 ISA Support",
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153 [FeatureMips64r3, FeatureMips32r5]>;
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154 def FeatureMips64r6 : SubtargetFeature<"mips64r6", "MipsArchVersion",
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155 "Mips64r6",
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156 "Mips64r6 ISA Support [experimental]",
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95
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157 [FeatureMips32r6, FeatureMips64r5,
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77
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158 FeatureNaN2008]>;
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121
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159 def FeatureSym32 : SubtargetFeature<"sym32", "HasSym32", "true",
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160 "Symbols are 32 bit on Mips64">;
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161
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162 def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true",
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163 "Mips16 mode">;
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164
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165 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
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166 def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
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167 "Mips DSP-R2 ASE", [FeatureDSP]>;
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95
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168 def FeatureDSPR3
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169 : SubtargetFeature<"dspr3", "HasDSPR3", "true", "Mips DSP-R3 ASE",
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170 [ FeatureDSP, FeatureDSPR2 ]>;
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171
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172 def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
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173
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174 def FeatureEVA : SubtargetFeature<"eva", "HasEVA", "true", "Mips EVA ASE">;
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175
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176 def FeatureMicroMips : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
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177 "microMips mode">;
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178
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77
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179 def FeatureCnMips : SubtargetFeature<"cnmips", "HasCnMips",
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180 "true", "Octeon cnMIPS Support",
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181 [FeatureMips64r2]>;
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182
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183 def FeatureUseTCCInDIV : SubtargetFeature<
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184 "use-tcc-in-div",
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185 "UseTCCInDIV", "false",
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186 "Force the assembler to use trapping">;
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187
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121
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188 def FeatureMadd4 : SubtargetFeature<"nomadd4", "DisableMadd4", "true",
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189 "Disable 4-operand madd.fmt and related instructions">;
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190
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191 def FeatureMT : SubtargetFeature<"mt", "HasMT", "true", "Mips MT ASE">;
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192
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193 def FeatureLongCalls : SubtargetFeature<"long-calls", "UseLongCalls", "true",
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194 "Disable use of the jal instruction">;
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195
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196 //===----------------------------------------------------------------------===//
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197 // Mips processors supported.
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198 //===----------------------------------------------------------------------===//
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199
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95
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200 def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
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201 "MipsSubtarget::CPU::P5600",
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202 "The P5600 Processor", [FeatureMips32r5]>;
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203
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204 class Proc<string Name, list<SubtargetFeature> Features>
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120
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205 : ProcessorModel<Name, MipsGenericModel, Features>;
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206
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83
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207 def : Proc<"mips1", [FeatureMips1]>;
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208 def : Proc<"mips2", [FeatureMips2]>;
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209 def : Proc<"mips32", [FeatureMips32]>;
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210 def : Proc<"mips32r2", [FeatureMips32r2]>;
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95
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211 def : Proc<"mips32r3", [FeatureMips32r3]>;
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212 def : Proc<"mips32r5", [FeatureMips32r5]>;
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83
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213 def : Proc<"mips32r6", [FeatureMips32r6]>;
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77
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214
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83
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215 def : Proc<"mips3", [FeatureMips3]>;
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216 def : Proc<"mips4", [FeatureMips4]>;
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217 def : Proc<"mips5", [FeatureMips5]>;
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218 def : Proc<"mips64", [FeatureMips64]>;
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219 def : Proc<"mips64r2", [FeatureMips64r2]>;
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95
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220 def : Proc<"mips64r3", [FeatureMips64r3]>;
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221 def : Proc<"mips64r5", [FeatureMips64r5]>;
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83
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222 def : Proc<"mips64r6", [FeatureMips64r6]>;
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223 def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>;
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95
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224 def : ProcessorModel<"p5600", MipsP5600Model, [ImplP5600]>;
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225
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226 def MipsAsmParser : AsmParser {
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227 let ShouldEmitMatchRegisterName = 0;
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228 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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229
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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230 def MipsAsmParserVariant : AsmParserVariant {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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231 int Variant = 0;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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232
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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233 // Recognize hard coded registers.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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234 string RegisterPrefix = "$";
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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235 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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236
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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237 def Mips : Target {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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238 let InstructionSet = MipsInstrInfo;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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239 let AssemblyParsers = [MipsAsmParser];
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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240 let AssemblyParserVariants = [MipsAsmParserVariant];
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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241 }
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