7
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1 \contentsline {chapter}{\numberline {第1章}研究目的と背景}{1}
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2 \contentsline {section}{\numberline {1.1}本論文の構成}{2}
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3 \contentsline {chapter}{\numberline {第2章}既存のマルチプラットフォームフレームワーク}{3}
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15
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4 \contentsline {section}{\numberline {2.1}Architecutre}{3}
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5 \contentsline {section}{\numberline {2.2}Shared Memory}{3}
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6 \contentsline {section}{\numberline {2.3}OpenCL}{5}
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7 \contentsline {section}{\numberline {2.4}CUDA}{7}
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8 \contentsline {section}{\numberline {2.5}StarPU}{8}
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13
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9 \contentsline {chapter}{\numberline {第3章}Cerium}{10}
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10 \contentsline {section}{\numberline {3.1}Cerium の概要}{10}
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11 \contentsline {section}{\numberline {3.2}Cerium TaskManager}{10}
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12 \contentsline {section}{\numberline {3.3}Cerium における Task}{11}
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13 \contentsline {section}{\numberline {3.4}Task の Scheduling}{11}
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14 \contentsline {section}{\numberline {3.5}Task 生成の例}{12}
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15 \contentsline {chapter}{\numberline {第4章}Ceriumを用いた例題}{14}
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16 \contentsline {section}{\numberline {4.1}Bitonic Sort}{14}
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17 \contentsline {section}{\numberline {4.2}Word Count}{16}
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18 \contentsline {section}{\numberline {4.3}FFT}{18}
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19 \contentsline {chapter}{\numberline {第5章}マルチコアへの対応}{19}
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20 \contentsline {section}{\numberline {5.1}マルチコア上での実行の機構}{19}
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15
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21 \contentsline {section}{\numberline {5.2}DMA}{19}
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22 \contentsline {chapter}{\numberline {第6章}GPGPU への対応}{20}
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23 \contentsline {section}{\numberline {6.1}OpenCL および CUDA による実装}{20}
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24 \contentsline {section}{\numberline {6.2}データ並列}{21}
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25 \contentsline {chapter}{\numberline {第7章}並列処理向けI/O}{24}
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16
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26 \contentsline {section}{\numberline {7.1}mmap}{24}
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27 \contentsline {section}{\numberline {7.2}Blocked Read による I/O の並列化}{25}
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28 \contentsline {section}{\numberline {7.3}I/O 専用 Thread の実装}{27}
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29 \contentsline {chapter}{\numberline {第8章}Memory Allocator}{28}
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30 \contentsline {section}{\numberline {8.1}現状のMemory Allocator}{28}
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31 \contentsline {section}{\numberline {8.2}新しいMemory Allocator}{28}
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32 \contentsline {chapter}{\numberline {第9章}ベンチマーク}{29}
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33 \contentsline {section}{\numberline {9.1}実験環境}{29}
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34 \contentsline {section}{\numberline {9.2}マルチコア}{30}
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35 \contentsline {section}{\numberline {9.3}GPGPU}{30}
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36 \contentsline {section}{\numberline {9.4}並列 I/O}{30}
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37 \contentsline {chapter}{\numberline {第10章}結論}{32}
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38 \contentsline {section}{\numberline {10.1}まとめ}{32}
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39 \contentsline {section}{\numberline {10.2}今後の課題}{32}
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40 \contentsline {chapter}{謝辞}{33}
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41 \contentsline {chapter}{参考文献}{34}
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42 \contentsline {chapter}{発表文献}{35}
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