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annotate llvm/test/TableGen/dag-isel-subregs.td @ 207:2e18cbf3894f

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LLVM12
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Tue, 08 Jun 2021 06:07:14 +0900
parents 1d019706d866
children
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1 // RUN: llvm-tblgen -gen-dag-isel -I %p/../../include -I %p/Common %s | FileCheck %s
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3 include "reg-with-subregs-common.td"
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5 // CHECK-LABEL: OPC_CheckOpcode, TARGET_VAL(ISD::EXTRACT_SUBVECTOR),
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6 // CHECK: OPC_CheckChild1Integer, 0,
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7 // CHECK: OPC_EmitStringInteger, MVT::i32, sub0_sub1,
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8 def : Pat<(v2i32 (extract_subvector v32i32:$src, (i32 0))),
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9 (EXTRACT_SUBREG GPR_1024:$src, sub0_sub1)>;
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10
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11 // CHECK: OPC_CheckChild1Integer, 30,
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12 // CHECK: OPC_EmitInteger, MVT::i32, 10|128,2/*266*/,
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13 def : Pat<(v2i32 (extract_subvector v32i32:$src, (i32 15))),
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14 (EXTRACT_SUBREG GPR_1024:$src, sub30_sub31)>;