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annotate level1/modules/dwread.asm @ 3030:41d88c40b023

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Updated becker port routine with a timeout check. Updated becker port routine was provided by: Brett Gordon
author David Ladd <drencor-xeen@users.sf.net>
date Fri, 19 Dec 2014 19:26:42 -0600
parents 28ed72477814
children 75bf8852c390
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0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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1 *******************************************************
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2 *
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3 * DWRead
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4 * Receive a response from the DriveWire server.
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5 * Times out if serial port goes idle for more than 1.4 (0.7) seconds.
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6 * Serial data format: 1-8-N-1
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7 * 4/12/2009 by Darren Atkinson
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8 *
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9 * Entry:
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10 * X = starting address where data is to be stored
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11 * Y = number of bytes expected
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12 *
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13 * Exit:
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14 * CC = carry set on framing error, Z set if all bytes received
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15 * X = starting address of data received
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16 * Y = checksum
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17 * U is preserved. All accumulators are clobbered
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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18 *
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19
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20 IFNE ARDUINO
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21 * Note: this is an optimistic routine. It presumes that the server will always be there, and
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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22 * has NO timeout fallback. It is also very short and quick.
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ce3dba57003b boot_dw now uses dwinit.asm.
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23 DWRead clra ; clear Carry (no framing error)
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24 pshs u,x,cc ; preserve registers
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25 leau ,x
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26 ldx #$0000
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ce3dba57003b boot_dw now uses dwinit.asm.
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27 loop@ tst $FF51 ; check for CA1 bit (1=Arduino has byte ready)
ce3dba57003b boot_dw now uses dwinit.asm.
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28 bpl loop@ ; loop if not set
ce3dba57003b boot_dw now uses dwinit.asm.
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29 ldb $FF50 ; clear CA1 bit in status register
ce3dba57003b boot_dw now uses dwinit.asm.
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30 stb ,u+ ; save off acquired byte
ce3dba57003b boot_dw now uses dwinit.asm.
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31 abx ; update checksum
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32 leay ,-y
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33 bne loop@
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34 leay ,x ; return checksum in Y
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35 puls cc,x,u,pc ; restore registers and return
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36
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37 ELSE
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38
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39 IFNE JMCPBCK
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40 * NOTE: There is no timeout currently on here...
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41 DWRead clra ; clear Carry (no framing error)
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42 deca ; clear Z flag, A = timeout msb ($ff)
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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43 tfr cc,b
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44 pshs u,x,dp,b,a ; preserve registers, push timeout msb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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45 leau ,x
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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46 ldx #$0000
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47 orcc #IntMasks
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48 loop@ ldb $FF4C
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49 bitb #$02
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50 beq loop@
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51 ldb $FF44
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52 stb ,u+
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53 abx
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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54 leay ,-y
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55 bne loop@
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56
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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57 tfr x,y
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58 ldb #0
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59 lda #3
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60 leas 1,s ; remove timeout msb from stack
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61 inca ; A = status to be returned in C and Z
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62 ora ,s ; place status information into the..
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63 sta ,s ; ..C and Z bits of the preserved CC
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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64 leay ,x ; return checksum in Y
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65 puls cc,dp,x,u,pc ; restore registers and return
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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66 ELSE
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67 IFNE BECKER
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68 * NOTE: There is no timeout currently on here...
3030
41d88c40b023 Updated becker port routine with a timeout check.
David Ladd <drencor-xeen@users.sf.net>
parents: 2898
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69 DWRead clra ; clear Carry, Set Z
41d88c40b023 Updated becker port routine with a timeout check.
David Ladd <drencor-xeen@users.sf.net>
parents: 2898
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70 pshs cc,x,u ; save regs
41d88c40b023 Updated becker port routine with a timeout check.
David Ladd <drencor-xeen@users.sf.net>
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71 leau ,x ; U is data buffer
41d88c40b023 Updated becker port routine with a timeout check.
David Ladd <drencor-xeen@users.sf.net>
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72 ldx #$0000 ; X is reset check sum
41d88c40b023 Updated becker port routine with a timeout check.
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73 IFEQ NOINTMASK
41d88c40b023 Updated becker port routine with a timeout check.
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74 orcc #IntMasks ; turn off interrupts
41d88c40b023 Updated becker port routine with a timeout check.
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75 ENDC
41d88c40b023 Updated becker port routine with a timeout check.
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76 ini@ pshs x ; save X
41d88c40b023 Updated becker port routine with a timeout check.
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77 ldx #0x8000 ; X = timeout
41d88c40b023 Updated becker port routine with a timeout check.
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78 loop@ ldb $FF41 ; test for data ready flag
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79 bitb #$02
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41d88c40b023 Updated becker port routine with a timeout check.
David Ladd <drencor-xeen@users.sf.net>
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80 bne rdy@ ; byte is ready
41d88c40b023 Updated becker port routine with a timeout check.
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81 leax -1,x ; bump timout
41d88c40b023 Updated becker port routine with a timeout check.
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82 bne loop@ ; not timed out, try again
41d88c40b023 Updated becker port routine with a timeout check.
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83 ;; timed out!
41d88c40b023 Updated becker port routine with a timeout check.
David Ladd <drencor-xeen@users.sf.net>
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84 puls x ; remove timeout off stack
41d88c40b023 Updated becker port routine with a timeout check.
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85 puls cc ; pull CC
41d88c40b023 Updated becker port routine with a timeout check.
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86 comb ; reset Z (timeout error)
41d88c40b023 Updated becker port routine with a timeout check.
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87 puls x,u,pc ; restore registers and return
41d88c40b023 Updated becker port routine with a timeout check.
David Ladd <drencor-xeen@users.sf.net>
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88 ;; a byte is ready
41d88c40b023 Updated becker port routine with a timeout check.
David Ladd <drencor-xeen@users.sf.net>
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89 rdy@ puls x ; restore X
41d88c40b023 Updated becker port routine with a timeout check.
David Ladd <drencor-xeen@users.sf.net>
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90 ldb $FF42 ; get byte from port
41d88c40b023 Updated becker port routine with a timeout check.
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91 stb ,u+ ; store in data buffer
41d88c40b023 Updated becker port routine with a timeout check.
David Ladd <drencor-xeen@users.sf.net>
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92 abx ; add received byte to checksum
41d88c40b023 Updated becker port routine with a timeout check.
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93 leay ,-y ; decrement byte counter
41d88c40b023 Updated becker port routine with a timeout check.
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94 bne ini@ ; go get another byte if not done
41d88c40b023 Updated becker port routine with a timeout check.
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95 ;; done reading bytes return
41d88c40b023 Updated becker port routine with a timeout check.
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96 tfr x,y ; put checksum in y
41d88c40b023 Updated becker port routine with a timeout check.
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97 puls cc,x,u,pc ; restore registers and return
2772
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98 ENDC
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99 ENDC
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100
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101 IFEQ BECKER+JMCPBCK+ARDUINO
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102 IFNE BAUD38400
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103 *******************************************************
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104 * 38400 bps using 6809 code and timimg
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105 *******************************************************
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106
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107 DWRead clra ; clear Carry (no framing error)
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108 deca ; clear Z flag, A = timeout msb ($ff)
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109 tfr cc,b
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110 pshs u,x,dp,b,a ; preserve registers, push timeout msb
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111 orcc #$50 ; mask interrupts
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112 tfr a,dp ; set direct page to $FFxx
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113 setdp $ff
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114 leau ,x ; U = storage ptr
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115 ldx #0 ; initialize checksum
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116 adda #2 ; A = $01 (serial in mask), set Carry
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117
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118 * Wait for a start bit or timeout
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119 rx0010 bcc rxExit ; exit if timeout expired
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120 ldb #$ff ; init timeout lsb
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121 rx0020 bita <BBIN ; check for start bit
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122 beq rxByte ; branch if start bit detected
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123 subb #1 ; decrement timeout lsb
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124 bita <BBIN
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125 beq rxByte
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126 bcc rx0020 ; loop until timeout lsb rolls under
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
127 bita <BBIN
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
128 beq rxByte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
129 addb ,s ; B = timeout msb - 1
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
130 bita <BBIN
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
131 beq rxByte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
132 stb ,s ; store decremented timeout msb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
133 bita <BBIN
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
134 bne rx0010 ; loop if still no start bit
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
135
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
136 * Read a byte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
137 rxByte leay ,-y ; decrement request count
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
138 ldd #$ff80 ; A = timeout msb, B = shift counter
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
139 sta ,s ; reset timeout msb for next byte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
140 rx0030 exg a,a
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
141 nop
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
142 lda <BBIN ; read data bit
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
143 lsra ; shift into carry
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
144 rorb ; rotate into byte accumulator
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
145 lda #$01 ; prep stop bit mask
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
146 bcc rx0030 ; loop until all 8 bits read
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
147
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
148 stb ,u+ ; store received byte to memory
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
149 abx ; update checksum
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
150 ldb #$ff ; set timeout lsb for next byte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
151 anda <BBIN ; read stop bit
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
152 beq rxExit ; exit if framing error
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
153 leay ,y ; test request count
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
154 bne rx0020 ; loop if another byte wanted
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
155 lda #$03 ; setup to return SUCCESS
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
156
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
157 * Clean up, set status and return
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
158 rxExit leas 1,s ; remove timeout msb from stack
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
159 inca ; A = status to be returned in C and Z
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
160 ora ,s ; place status information into the..
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
161 sta ,s ; ..C and Z bits of the preserved CC
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
162 leay ,x ; return checksum in Y
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
163 puls cc,dp,x,u,pc ; restore registers and return
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
164 setdp $00
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
165
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
166
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
167 ELSE
2770
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
168 IFEQ H6309
2772
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
169 *******************************************************
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
170 * 57600 (115200) bps using 6809 code and timimg
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
171 *******************************************************
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
172
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
173 DWRead clra ; clear Carry (no framing error)
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
174 deca ; clear Z flag, A = timeout msb ($ff)
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
175 tfr cc,b
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
176 pshs u,x,dp,b,a ; preserve registers, push timeout msb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
177 orcc #$50 ; mask interrupts
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
178 tfr a,dp ; set direct page to $FFxx
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
179 setdp $ff
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
180 leau ,x ; U = storage ptr
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
181 ldx #0 ; initialize checksum
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
182 lda #$01 ; A = serial in mask
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
183 bra rx0030 ; go wait for start bit
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
184
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
185 * Read a byte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
186 rxByte leau 1,u ; bump storage ptr
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
187 leay ,-y ; decrement request count
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
188 lda <BBIN ; read bit 0
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
189 lsra ; move bit 0 into Carry
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
190 ldd #$ff20 ; A = timeout msb, B = shift counter
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
191 sta ,s ; reset timeout msb for next byte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
192 rorb ; rotate bit 0 into byte accumulator
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
193 rx0010 lda <BBIN ; read bit (d1, d3, d5)
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
194 lsra
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
195 rorb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
196 bita 1,s ; 5 cycle delay
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
197 bcs rx0020 ; exit loop after reading bit 5
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
198 lda <BBIN ; read bit (d2, d4)
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
199 lsra
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
200 rorb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
201 leau ,u
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
202 bra rx0010
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
203
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
204 rx0020 lda <BBIN ; read bit 6
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
205 lsra
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
206 rorb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
207 leay ,y ; test request count
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
208 beq rx0050 ; branch if final byte of request
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
209 lda <BBIN ; read bit 7
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
210 lsra
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
211 rorb ; byte is now complete
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
212 stb -1,u ; store received byte to memory
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
213 abx ; update checksum
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
214 lda <BBIN ; read stop bit
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
215 anda #$01 ; mask out other bits
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
216 beq rxExit ; exit if framing error
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
217
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
218 * Wait for a start bit or timeout
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
219 rx0030 bita <BBIN ; check for start bit
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
220 beq rxByte ; branch if start bit detected
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
221 bita <BBIN ; again
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
222 beq rxByte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
223 ldb #$ff ; init timeout lsb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
224 rx0040 bita <BBIN
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
225 beq rxByte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
226 subb #1 ; decrement timeout lsb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
227 bita <BBIN
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
228 beq rxByte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
229 bcc rx0040 ; loop until timeout lsb rolls under
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
230 bita <BBIN
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
231 beq rxByte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
232 addb ,s ; B = timeout msb - 1
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
233 bita <BBIN
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
234 beq rxByte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
235 stb ,s ; store decremented timeout msb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
236 bita <BBIN
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
237 beq rxByte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
238 bcs rx0030 ; loop if timeout hasn't expired
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
239 bra rxExit ; exit due to timeout
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
240
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
241 rx0050 lda <BBIN ; read bit 7 of final byte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
242 lsra
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
243 rorb ; byte is now complete
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
244 stb -1,u ; store received byte to memory
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
245 abx ; calculate final checksum
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
246 lda <BBIN ; read stop bit
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
247 anda #$01 ; mask out other bits
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
248 ora #$02 ; return SUCCESS if no framing error
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
249
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
250 * Clean up, set status and return
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
251 rxExit leas 1,s ; remove timeout msb from stack
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
252 inca ; A = status to be returned in C and Z
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
253 ora ,s ; place status information into the..
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
254 sta ,s ; ..C and Z bits of the preserved CC
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
255 leay ,x ; return checksum in Y
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
256 puls cc,dp,x,u,pc ; restore registers and return
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
257 setdp $00
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
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258
2770
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Boisy Pitre <boisy.pitre@nuance.com>
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259
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Boisy Pitre <boisy.pitre@nuance.com>
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260 ELSE
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Boisy Pitre <boisy.pitre@nuance.com>
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261 *******************************************************
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
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262 * 57600 (115200) bps using 6309 native mode
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
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263 *******************************************************
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
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264
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
265 DWRead clrb ; clear Carry (no framing error)
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
266 decb ; clear Z flag, B = $FF
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
267 pshs u,x,dp,cc ; preserve registers
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
268 orcc #$50 ; mask interrupts
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
269 * ldmd #1 ; requires 6309 native mode
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
270 tfr b,dp ; set direct page to $FFxx
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
271 setdp $ff
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
272 leay -1,y ; adjust request count
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
273 leau ,x ; U = storage ptr
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
274 tfr 0,x ; initialize checksum
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
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275 lda #$01 ; A = serial in mask
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Boisy Pitre <boisy.pitre@nuance.com>
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diff changeset
276 bra rx0030 ; go wait for start bit
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
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277
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
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278 * Read a byte
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Boisy Pitre <boisy.pitre@nuance.com>
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diff changeset
279 rxByte sexw ; 4 cycle delay
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Boisy Pitre <boisy.pitre@nuance.com>
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diff changeset
280 ldw #$006a ; shift counter and timing flags
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Boisy Pitre <boisy.pitre@nuance.com>
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diff changeset
281 clra ; clear carry so next will branch
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
282 rx0010 bcc rx0020 ; branch if even bit number (15 cycles)
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Boisy Pitre <boisy.pitre@nuance.com>
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diff changeset
283 nop ; extra (16th) cycle
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
284 rx0020 lda <BBIN ; read bit
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
285 lsra ; move bit into carry
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
286 rorb ; rotate bit into byte accumulator
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
287 lda #0 ; prep A for 8th data bit
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
288 lsrw ; bump shift count, timing bit to carry
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
289 bne rx0010 ; loop until 7th data bit has been read
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
290 incw ; W = 1 for subtraction from Y
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
291 inca ; A = 1 for reading bit 7
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
292 anda <BBIN ; read bit 7
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
293 lsra ; move bit 7 into carry, A = 0
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
294 rorb ; byte is now complete
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
295 stb ,u+ ; store received byte to memory
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
296 abx ; update checksum
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
297 subr w,y ; decrement request count
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
298 inca ; A = 1 for reading stop bit
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
299 anda <BBIN ; read stop bit
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
300 bls rxExit ; exit if completed or framing error
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
301
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
302 * Wait for a start bit or timeout
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
303 rx0030 clrw ; initialize timeout counter
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
304 rx0040 bita <BBIN ; check for start bit
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
305 beq rxByte ; branch if start bit detected
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
306 addw #1 ; bump timeout counter
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
307 bita <BBIN
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
308 beq rxByte
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
309 bcc rx0040 ; loop until timeout rolls over
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Boisy Pitre <boisy.pitre@nuance.com>
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diff changeset
310 lda #$03 ; setup to return TIMEOUT status
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
311
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
312 * Clean up, set status and return
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Boisy Pitre <boisy.pitre@nuance.com>
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diff changeset
313 rxExit beq rx0050 ; branch if framing error
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
314 eora #$02 ; toggle SUCCESS flag
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
315 rx0050 inca ; A = status to be returned in C and Z
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
316 ora ,s ; place status information into the..
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
317 sta ,s ; ..C and Z bits of the preserved CC
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
318 leay ,x ; return checksum in Y
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
319 puls cc,dp,x,u,pc ; restore registers and return
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
320 setdp $00
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Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
321
2772
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
322 ENDC
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
323 ENDC
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
324 ENDC
2770
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Boisy Pitre <boisy.pitre@nuance.com>
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diff changeset
325 ENDC