0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1 //===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
3 // The LLVM Compiler Infrastructure
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
4 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
5 // This file is distributed under the University of Illinois Open Source
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
6 // License. See LICENSE.TXT for details.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
7 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
8 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
9 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
10 // This file implements the Mips specific subclass of TargetSubtargetInfo.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
11 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
12 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
13
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
14 #include "MipsMachineFunction.h"
|
|
77
|
15 #include "Mips.h"
|
|
|
16 #include "MipsRegisterInfo.h"
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
17 #include "MipsSubtarget.h"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
18 #include "MipsTargetMachine.h"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
19 #include "llvm/IR/Attributes.h"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
20 #include "llvm/IR/Function.h"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
21 #include "llvm/Support/CommandLine.h"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
22 #include "llvm/Support/Debug.h"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
23 #include "llvm/Support/TargetRegistry.h"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
24 #include "llvm/Support/raw_ostream.h"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
25
|
|
77
|
26 using namespace llvm;
|
|
|
27
|
|
|
28 #define DEBUG_TYPE "mips-subtarget"
|
|
|
29
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
30 #define GET_SUBTARGETINFO_TARGET_DESC
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
31 #define GET_SUBTARGETINFO_CTOR
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
32 #include "MipsGenSubtargetInfo.inc"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
33
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
34 // FIXME: Maybe this should be on by default when Mips16 is specified
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
35 //
|
|
95
|
36 static cl::opt<bool>
|
|
|
37 Mixed16_32("mips-mixed-16-32", cl::init(false),
|
|
|
38 cl::desc("Allow for a mixture of Mips16 "
|
|
|
39 "and Mips32 code in a single output file"),
|
|
|
40 cl::Hidden);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
41
|
|
95
|
42 static cl::opt<bool> Mips_Os16("mips-os16", cl::init(false),
|
|
|
43 cl::desc("Compile all functions that don't use "
|
|
|
44 "floating point as Mips 16"),
|
|
|
45 cl::Hidden);
|
|
|
46
|
|
|
47 static cl::opt<bool> Mips16HardFloat("mips16-hard-float", cl::NotHidden,
|
|
|
48 cl::desc("Enable mips16 hard float."),
|
|
|
49 cl::init(false));
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
50
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
51 static cl::opt<bool>
|
|
95
|
52 Mips16ConstantIslands("mips16-constant-islands", cl::NotHidden,
|
|
|
53 cl::desc("Enable mips16 constant islands."),
|
|
|
54 cl::init(true));
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
55
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
56 static cl::opt<bool>
|
|
95
|
57 GPOpt("mgpopt", cl::Hidden,
|
|
|
58 cl::desc("Enable gp-relative addressing of mips small data items"));
|
|
77
|
59
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
60 void MipsSubtarget::anchor() { }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
61
|
|
95
|
62 MipsSubtarget::MipsSubtarget(const Triple &TT, const std::string &CPU,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
63 const std::string &FS, bool little,
|
|
83
|
64 const MipsTargetMachine &TM)
|
|
|
65 : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
|
|
95
|
66 IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false),
|
|
|
67 NoABICalls(false), IsFP64bit(false), UseOddSPReg(true),
|
|
|
68 IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
|
|
|
69 HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
|
|
|
70 HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
|
|
83
|
71 InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
|
|
95
|
72 HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16),
|
|
|
73 Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasEVA(false), TM(TM),
|
|
|
74 TargetTriple(TT), TSInfo(),
|
|
83
|
75 InstrInfo(
|
|
|
76 MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
|
|
77
|
77 FrameLowering(MipsFrameLowering::create(*this)),
|
|
83
|
78 TLInfo(MipsTargetLowering::create(TM, *this)) {
|
|
33
|
79
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
80 PreviousInMips16Mode = InMips16Mode;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
81
|
|
83
|
82 if (MipsArchVersion == MipsDefault)
|
|
|
83 MipsArchVersion = Mips32;
|
|
|
84
|
|
|
85 // Don't even attempt to generate code for MIPS-I and MIPS-V. They have not
|
|
|
86 // been tested and currently exist for the integrated assembler only.
|
|
77
|
87 if (MipsArchVersion == Mips1)
|
|
|
88 report_fatal_error("Code generation for MIPS-I is not implemented", false);
|
|
|
89 if (MipsArchVersion == Mips5)
|
|
|
90 report_fatal_error("Code generation for MIPS-V is not implemented", false);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
91
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
92 // Check if Architecture and ABI are compatible.
|
|
77
|
93 assert(((!isGP64bit() && (isABI_O32() || isABI_EABI())) ||
|
|
|
94 (isGP64bit() && (isABI_N32() || isABI_N64()))) &&
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
95 "Invalid Arch & ABI pair.");
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
96
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
97 if (hasMSA() && !isFP64bit())
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
98 report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). "
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
99 "See -mattr=+fp64.",
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
100 false);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
101
|
|
77
|
102 if (!isABI_O32() && !useOddSPReg())
|
|
|
103 report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false);
|
|
|
104
|
|
|
105 if (IsFPXX && (isABI_N32() || isABI_N64()))
|
|
|
106 report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false);
|
|
|
107
|
|
|
108 if (hasMips32r6()) {
|
|
|
109 StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
|
|
|
110
|
|
|
111 assert(isFP64bit());
|
|
|
112 assert(isNaN2008());
|
|
|
113 if (hasDSP())
|
|
|
114 report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
|
|
|
115 }
|
|
|
116
|
|
83
|
117 if (NoABICalls && TM.getRelocationModel() == Reloc::PIC_)
|
|
|
118 report_fatal_error("position-independent code requires '-mabicalls'");
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
119
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
120 // Set UseSmallSection.
|
|
83
|
121 UseSmallSection = GPOpt;
|
|
|
122 if (!NoABICalls && GPOpt) {
|
|
|
123 errs() << "warning: cannot use small-data accesses for '-mabicalls'"
|
|
|
124 << "\n";
|
|
|
125 UseSmallSection = false;
|
|
|
126 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
127 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
128
|
|
77
|
129 /// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
|
|
95
|
130 bool MipsSubtarget::enablePostRAScheduler() const { return true; }
|
|
77
|
131
|
|
|
132 void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
133 CriticalPathRCs.clear();
|
|
77
|
134 CriticalPathRCs.push_back(isGP64bit() ?
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
135 &Mips::GPR64RegClass : &Mips::GPR32RegClass);
|
|
77
|
136 }
|
|
|
137
|
|
|
138 CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
|
|
|
139 return CodeGenOpt::Aggressive;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
140 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
141
|
|
77
|
142 MipsSubtarget &
|
|
|
143 MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
|
|
83
|
144 const TargetMachine &TM) {
|
|
|
145 std::string CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU);
|
|
|
146
|
|
77
|
147 // Parse features string.
|
|
|
148 ParseSubtargetFeatures(CPUName, FS);
|
|
|
149 // Initialize scheduling itinerary for the specified CPU.
|
|
|
150 InstrItins = getInstrItineraryForCPU(CPUName);
|
|
|
151
|
|
95
|
152 if (InMips16Mode && !IsSoftFloat)
|
|
77
|
153 InMips16HardFloat = true;
|
|
|
154
|
|
|
155 return *this;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
156 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
157
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
158 bool MipsSubtarget::useConstantIslands() {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
159 DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands << "\n");
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
160 return Mips16ConstantIslands;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
161 }
|
|
77
|
162
|
|
|
163 Reloc::Model MipsSubtarget::getRelocationModel() const {
|
|
83
|
164 return TM.getRelocationModel();
|
|
77
|
165 }
|
|
83
|
166
|
|
|
167 bool MipsSubtarget::isABI_EABI() const { return getABI().IsEABI(); }
|
|
|
168 bool MipsSubtarget::isABI_N64() const { return getABI().IsN64(); }
|
|
|
169 bool MipsSubtarget::isABI_N32() const { return getABI().IsN32(); }
|
|
|
170 bool MipsSubtarget::isABI_O32() const { return getABI().IsO32(); }
|
|
|
171 const MipsABIInfo &MipsSubtarget::getABI() const { return TM.getABI(); }
|
