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annotate level1/modules/dwread.asm @ 3034:f818de1b815a

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Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup. Reasoning for this is on slower DW servers the return packets may not come back in time and would generate timeouts often. This prevented a few people being able to actually use the becker interface on those slower DW servers.
author David Ladd <drencor-xeen@users.sf.net>
date Sat, 03 Jan 2015 00:02:16 -0600
parents 75bf8852c390
children a47ee8f14eb8
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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2772
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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parents: 2771
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1 *******************************************************
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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2 *
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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3 * DWRead
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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4 * Receive a response from the DriveWire server.
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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5 * Times out if serial port goes idle for more than 1.4 (0.7) seconds.
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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6 * Serial data format: 1-8-N-1
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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7 * 4/12/2009 by Darren Atkinson
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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8 *
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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9 * Entry:
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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10 * X = starting address where data is to be stored
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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11 * Y = number of bytes expected
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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12 *
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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13 * Exit:
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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14 * CC = carry set on framing error, Z set if all bytes received
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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15 * X = starting address of data received
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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16 * Y = checksum
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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17 * U is preserved. All accumulators are clobbered
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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18 *
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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19
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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20 IFNE ARDUINO
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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21 * Note: this is an optimistic routine. It presumes that the server will always be there, and
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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22 * has NO timeout fallback. It is also very short and quick.
2773
ce3dba57003b boot_dw now uses dwinit.asm.
Boisy Pitre <boisy.pitre@nuance.com>
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23 DWRead clra ; clear Carry (no framing error)
2772
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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24 pshs u,x,cc ; preserve registers
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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25 leau ,x
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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26 ldx #$0000
2773
ce3dba57003b boot_dw now uses dwinit.asm.
Boisy Pitre <boisy.pitre@nuance.com>
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27 loop@ tst $FF51 ; check for CA1 bit (1=Arduino has byte ready)
ce3dba57003b boot_dw now uses dwinit.asm.
Boisy Pitre <boisy.pitre@nuance.com>
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28 bpl loop@ ; loop if not set
ce3dba57003b boot_dw now uses dwinit.asm.
Boisy Pitre <boisy.pitre@nuance.com>
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29 ldb $FF50 ; clear CA1 bit in status register
ce3dba57003b boot_dw now uses dwinit.asm.
Boisy Pitre <boisy.pitre@nuance.com>
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30 stb ,u+ ; save off acquired byte
ce3dba57003b boot_dw now uses dwinit.asm.
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31 abx ; update checksum
2772
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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32 leay ,-y
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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33 bne loop@
2773
ce3dba57003b boot_dw now uses dwinit.asm.
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34 leay ,x ; return checksum in Y
ce3dba57003b boot_dw now uses dwinit.asm.
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35 puls cc,x,u,pc ; restore registers and return
2772
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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36
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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37 ELSE
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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38
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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39 IFNE JMCPBCK
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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40 * NOTE: There is no timeout currently on here...
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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parents: 2771
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41 DWRead clra ; clear Carry (no framing error)
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
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42 deca ; clear Z flag, A = timeout msb ($ff)
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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43 tfr cc,b
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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44 pshs u,x,dp,b,a ; preserve registers, push timeout msb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
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45 leau ,x
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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46 ldx #$0000
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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47 orcc #IntMasks
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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48 loop@ ldb $FF4C
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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49 bitb #$02
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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50 beq loop@
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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51 ldb $FF44
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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52 stb ,u+
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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parents: 2771
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53 abx
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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parents: 2771
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54 leay ,-y
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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55 bne loop@
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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56
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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57 tfr x,y
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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58 ldb #0
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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59 lda #3
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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60 leas 1,s ; remove timeout msb from stack
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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parents: 2771
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61 inca ; A = status to be returned in C and Z
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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parents: 2771
diff changeset
62 ora ,s ; place status information into the..
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
63 sta ,s ; ..C and Z bits of the preserved CC
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
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64 leay ,x ; return checksum in Y
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
65 puls cc,dp,x,u,pc ; restore registers and return
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
66 ELSE
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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parents: 2771
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67 IFNE BECKER
3034
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
68 * NOTE: There is no timeout currently on here...
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
69 DWRead clra ; clear Carry (no framing error)
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
70 deca ; clear Z flag, A = timeout msb ($ff)
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
71 tfr cc,b
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
72 pshs u,x,dp,b,a ; preserve registers, push timeout msb
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
73 leau ,x
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
74 ldx #$0000
3030
41d88c40b023 Updated becker port routine with a timeout check.
David Ladd <drencor-xeen@users.sf.net>
parents: 2898
diff changeset
75 IFEQ NOINTMASK
3034
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
76 orcc #IntMasks
3030
41d88c40b023 Updated becker port routine with a timeout check.
David Ladd <drencor-xeen@users.sf.net>
parents: 2898
diff changeset
77 ENDC
3034
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
78 loop@ ldb $FF41
2772
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
79 bitb #$02
3034
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
80 beq loop@
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
81 ldb $FF42
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
82 stb ,u+
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
83 abx
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
84 leay ,-y
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
85 bne loop@
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
86 tfr x,y
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
87 ldb #0
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
88 lda #3
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
89 leas 1,s ; remove timeout msb from stack
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
90 inca ; A = status to be returned in C and Z
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
91 ora ,s ; place status information into the..
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
92 sta ,s ; ..C and Z bits of the preserved CC
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
93 leay ,x ; return checksum in Y
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
94 puls cc,dp,x,u,pc ; restore registers and return
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
95 ELSE
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
96 IFNE BECKERTO
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
97 * NOTE: There is now timeout ...
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
98 DWRead clra ; clear Carry, Set Z
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
99 pshs cc,x,u ; save regs
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
100 leau ,x ; U is data buffer
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
101 ldx #$0000 ; X is reset check sum
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
102 IFEQ NOINTMASK
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
103 orcc #IntMasks ; turn off interrupts
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
104 ENDC
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
105 ini@ pshs x ; save X
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
106 ldx #0x8000 ; X = timeout
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
107 loop@ ldb $FF41 ; test for data ready flag
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
108 bitb #$02
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
109 bne rdy@ ; byte is ready
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
110 leax -1,x ; bump timout
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
111 bne loop@ ; not timed out, try again
3030
41d88c40b023 Updated becker port routine with a timeout check.
David Ladd <drencor-xeen@users.sf.net>
parents: 2898
diff changeset
112 ;; timed out!
3034
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
113 puls x ; remove timeout off stack
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
114 puls cc ; pull CC
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
115 comb ; reset Z (timeout error)
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
116 puls x,u,pc ; restore registers and return
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
117 ;; a byte is ready
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
118 rdy@ puls x ; restore X
3030
41d88c40b023 Updated becker port routine with a timeout check.
David Ladd <drencor-xeen@users.sf.net>
parents: 2898
diff changeset
119 ldb $FF42 ; get byte from port
41d88c40b023 Updated becker port routine with a timeout check.
David Ladd <drencor-xeen@users.sf.net>
parents: 2898
diff changeset
120 stb ,u+ ; store in data buffer
41d88c40b023 Updated becker port routine with a timeout check.
David Ladd <drencor-xeen@users.sf.net>
parents: 2898
diff changeset
121 abx ; add received byte to checksum
41d88c40b023 Updated becker port routine with a timeout check.
David Ladd <drencor-xeen@users.sf.net>
parents: 2898
diff changeset
122 leay ,-y ; decrement byte counter
41d88c40b023 Updated becker port routine with a timeout check.
David Ladd <drencor-xeen@users.sf.net>
parents: 2898
diff changeset
123 bne ini@ ; go get another byte if not done
3034
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
124 ;; done reading bytes return
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
125 tfr x,y ; put checksum in y
3030
41d88c40b023 Updated becker port routine with a timeout check.
David Ladd <drencor-xeen@users.sf.net>
parents: 2898
diff changeset
126 puls cc,x,u,pc ; restore registers and return
3034
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
127
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
128 ENDC
2772
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
129 ENDC
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
130 ENDC
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
131
3034
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
132 IFEQ BECKER+JMCPBCK+ARDUINO+BECKERTO
2772
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
133 IFNE BAUD38400
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
134 *******************************************************
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
135 * 38400 bps using 6809 code and timimg
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
136 *******************************************************
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
137
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
138 DWRead clra ; clear Carry (no framing error)
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
139 deca ; clear Z flag, A = timeout msb ($ff)
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
140 tfr cc,b
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
141 pshs u,x,dp,b,a ; preserve registers, push timeout msb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
142 orcc #$50 ; mask interrupts
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
143 tfr a,dp ; set direct page to $FFxx
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
144 setdp $ff
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
145 leau ,x ; U = storage ptr
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
146 ldx #0 ; initialize checksum
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
147 adda #2 ; A = $01 (serial in mask), set Carry
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
148
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
149 * Wait for a start bit or timeout
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
150 rx0010 bcc rxExit ; exit if timeout expired
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
151 ldb #$ff ; init timeout lsb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
152 rx0020 bita <BBIN ; check for start bit
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
153 beq rxByte ; branch if start bit detected
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
154 subb #1 ; decrement timeout lsb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
155 bita <BBIN
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
156 beq rxByte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
157 bcc rx0020 ; loop until timeout lsb rolls under
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
158 bita <BBIN
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
159 beq rxByte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
160 addb ,s ; B = timeout msb - 1
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
161 bita <BBIN
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
162 beq rxByte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
163 stb ,s ; store decremented timeout msb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
164 bita <BBIN
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
165 bne rx0010 ; loop if still no start bit
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
166
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
167 * Read a byte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
168 rxByte leay ,-y ; decrement request count
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
169 ldd #$ff80 ; A = timeout msb, B = shift counter
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
170 sta ,s ; reset timeout msb for next byte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
171 rx0030 exg a,a
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
172 nop
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
173 lda <BBIN ; read data bit
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
174 lsra ; shift into carry
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
175 rorb ; rotate into byte accumulator
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
176 lda #$01 ; prep stop bit mask
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
177 bcc rx0030 ; loop until all 8 bits read
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
178
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
179 stb ,u+ ; store received byte to memory
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
180 abx ; update checksum
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
181 ldb #$ff ; set timeout lsb for next byte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
182 anda <BBIN ; read stop bit
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
183 beq rxExit ; exit if framing error
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
184 leay ,y ; test request count
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
185 bne rx0020 ; loop if another byte wanted
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
186 lda #$03 ; setup to return SUCCESS
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
187
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
188 * Clean up, set status and return
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
189 rxExit leas 1,s ; remove timeout msb from stack
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
190 inca ; A = status to be returned in C and Z
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
191 ora ,s ; place status information into the..
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
192 sta ,s ; ..C and Z bits of the preserved CC
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
193 leay ,x ; return checksum in Y
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
194 puls cc,dp,x,u,pc ; restore registers and return
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
195 setdp $00
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
196
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
197
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
198 ELSE
2770
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
199 IFEQ H6309
2772
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
200 *******************************************************
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
201 * 57600 (115200) bps using 6809 code and timimg
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
202 *******************************************************
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
203
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
204 DWRead clra ; clear Carry (no framing error)
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
205 deca ; clear Z flag, A = timeout msb ($ff)
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
206 tfr cc,b
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
207 pshs u,x,dp,b,a ; preserve registers, push timeout msb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
208 orcc #$50 ; mask interrupts
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
209 tfr a,dp ; set direct page to $FFxx
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
210 setdp $ff
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
211 leau ,x ; U = storage ptr
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
212 ldx #0 ; initialize checksum
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
213 lda #$01 ; A = serial in mask
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
214 bra rx0030 ; go wait for start bit
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
215
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
216 * Read a byte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
217 rxByte leau 1,u ; bump storage ptr
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
218 leay ,-y ; decrement request count
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
219 lda <BBIN ; read bit 0
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
220 lsra ; move bit 0 into Carry
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
221 ldd #$ff20 ; A = timeout msb, B = shift counter
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
222 sta ,s ; reset timeout msb for next byte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
223 rorb ; rotate bit 0 into byte accumulator
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
224 rx0010 lda <BBIN ; read bit (d1, d3, d5)
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
225 lsra
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
226 rorb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
227 bita 1,s ; 5 cycle delay
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
228 bcs rx0020 ; exit loop after reading bit 5
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
229 lda <BBIN ; read bit (d2, d4)
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
230 lsra
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
231 rorb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
232 leau ,u
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
233 bra rx0010
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
234
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
235 rx0020 lda <BBIN ; read bit 6
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
236 lsra
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
237 rorb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
238 leay ,y ; test request count
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
239 beq rx0050 ; branch if final byte of request
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
240 lda <BBIN ; read bit 7
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
241 lsra
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
242 rorb ; byte is now complete
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
243 stb -1,u ; store received byte to memory
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
244 abx ; update checksum
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
245 lda <BBIN ; read stop bit
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
246 anda #$01 ; mask out other bits
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
247 beq rxExit ; exit if framing error
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
248
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
249 * Wait for a start bit or timeout
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
250 rx0030 bita <BBIN ; check for start bit
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
251 beq rxByte ; branch if start bit detected
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
252 bita <BBIN ; again
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
253 beq rxByte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
254 ldb #$ff ; init timeout lsb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
255 rx0040 bita <BBIN
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
256 beq rxByte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
257 subb #1 ; decrement timeout lsb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
258 bita <BBIN
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
259 beq rxByte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
260 bcc rx0040 ; loop until timeout lsb rolls under
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
261 bita <BBIN
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
262 beq rxByte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
263 addb ,s ; B = timeout msb - 1
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
264 bita <BBIN
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
265 beq rxByte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
266 stb ,s ; store decremented timeout msb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
267 bita <BBIN
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
268 beq rxByte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
269 bcs rx0030 ; loop if timeout hasn't expired
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
270 bra rxExit ; exit due to timeout
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
271
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
272 rx0050 lda <BBIN ; read bit 7 of final byte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
273 lsra
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
274 rorb ; byte is now complete
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
275 stb -1,u ; store received byte to memory
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
276 abx ; calculate final checksum
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
277 lda <BBIN ; read stop bit
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
278 anda #$01 ; mask out other bits
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
279 ora #$02 ; return SUCCESS if no framing error
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
280
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
281 * Clean up, set status and return
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
282 rxExit leas 1,s ; remove timeout msb from stack
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
283 inca ; A = status to be returned in C and Z
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
284 ora ,s ; place status information into the..
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
285 sta ,s ; ..C and Z bits of the preserved CC
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
286 leay ,x ; return checksum in Y
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
287 puls cc,dp,x,u,pc ; restore registers and return
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
288 setdp $00
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
289
2770
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
290
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
291 ELSE
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
292 *******************************************************
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
293 * 57600 (115200) bps using 6309 native mode
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
294 *******************************************************
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
295
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
296 DWRead clrb ; clear Carry (no framing error)
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
297 decb ; clear Z flag, B = $FF
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
298 pshs u,x,dp,cc ; preserve registers
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
299 orcc #$50 ; mask interrupts
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
300 * ldmd #1 ; requires 6309 native mode
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
301 tfr b,dp ; set direct page to $FFxx
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
302 setdp $ff
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
303 leay -1,y ; adjust request count
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
304 leau ,x ; U = storage ptr
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
305 tfr 0,x ; initialize checksum
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
306 lda #$01 ; A = serial in mask
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
307 bra rx0030 ; go wait for start bit
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
308
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
309 * Read a byte
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
310 rxByte sexw ; 4 cycle delay
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
311 ldw #$006a ; shift counter and timing flags
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
312 clra ; clear carry so next will branch
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
313 rx0010 bcc rx0020 ; branch if even bit number (15 cycles)
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
314 nop ; extra (16th) cycle
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
315 rx0020 lda <BBIN ; read bit
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
316 lsra ; move bit into carry
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
317 rorb ; rotate bit into byte accumulator
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
318 lda #0 ; prep A for 8th data bit
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
319 lsrw ; bump shift count, timing bit to carry
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
320 bne rx0010 ; loop until 7th data bit has been read
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
321 incw ; W = 1 for subtraction from Y
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
322 inca ; A = 1 for reading bit 7
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
323 anda <BBIN ; read bit 7
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
324 lsra ; move bit 7 into carry, A = 0
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
325 rorb ; byte is now complete
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
326 stb ,u+ ; store received byte to memory
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
327 abx ; update checksum
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
328 subr w,y ; decrement request count
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
329 inca ; A = 1 for reading stop bit
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
330 anda <BBIN ; read stop bit
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
331 bls rxExit ; exit if completed or framing error
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
332
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
333 * Wait for a start bit or timeout
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
334 rx0030 clrw ; initialize timeout counter
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
335 rx0040 bita <BBIN ; check for start bit
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
336 beq rxByte ; branch if start bit detected
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
337 addw #1 ; bump timeout counter
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
338 bita <BBIN
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
339 beq rxByte
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
340 bcc rx0040 ; loop until timeout rolls over
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
341 lda #$03 ; setup to return TIMEOUT status
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
342
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
343 * Clean up, set status and return
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
344 rxExit beq rx0050 ; branch if framing error
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
345 eora #$02 ; toggle SUCCESS flag
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
346 rx0050 inca ; A = status to be returned in C and Z
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
347 ora ,s ; place status information into the..
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
348 sta ,s ; ..C and Z bits of the preserved CC
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
349 leay ,x ; return checksum in Y
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
350 puls cc,dp,x,u,pc ; restore registers and return
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
351 setdp $00
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
352
2772
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
353 ENDC
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
354 ENDC
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
355 ENDC
2770
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
356 ENDC