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annotate level1/modules/dwread.asm @ 3246:be3446f758ca

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Updated dwread.asm and dwwrite.asm so that the 6551 routines could have specially defined flags so that some of the addresses could be overridden by the make files if needed.
author David Ladd <drencor-xeen@users.sourceforge.net>
date Sun, 11 Mar 2018 01:30:30 -0600
parents a47ee8f14eb8
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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1 *******************************************************
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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2 *
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3 * DWRead
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4 * Receive a response from the DriveWire server.
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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5 * Times out if serial port goes idle for more than 1.4 (0.7) seconds.
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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6 * Serial data format: 1-8-N-1
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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7 * 4/12/2009 by Darren Atkinson
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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8 *
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9 * Entry:
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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10 * X = starting address where data is to be stored
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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11 * Y = number of bytes expected
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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12 *
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13 * Exit:
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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14 * CC = carry set on framing error, Z set if all bytes received
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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15 * X = starting address of data received
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16 * Y = checksum
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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17 * U is preserved. All accumulators are clobbered
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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18 *
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19
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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20 IFNE ARDUINO
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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21 * Note: this is an optimistic routine. It presumes that the server will always be there, and
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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22 * has NO timeout fallback. It is also very short and quick.
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ce3dba57003b boot_dw now uses dwinit.asm.
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23 DWRead clra ; clear Carry (no framing error)
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24 pshs u,x,cc ; preserve registers
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25 leau ,x
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26 ldx #$0000
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ce3dba57003b boot_dw now uses dwinit.asm.
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27 loop@ tst $FF51 ; check for CA1 bit (1=Arduino has byte ready)
ce3dba57003b boot_dw now uses dwinit.asm.
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28 bpl loop@ ; loop if not set
ce3dba57003b boot_dw now uses dwinit.asm.
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29 ldb $FF50 ; clear CA1 bit in status register
ce3dba57003b boot_dw now uses dwinit.asm.
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30 stb ,u+ ; save off acquired byte
ce3dba57003b boot_dw now uses dwinit.asm.
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31 abx ; update checksum
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32 leay ,-y
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33 bne loop@
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34 leay ,x ; return checksum in Y
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35 puls cc,x,u,pc ; restore registers and return
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36
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37 ELSE
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38
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a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
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39 IFNE SY6551N
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
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40 IFNDEF SY6551B
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
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41 SY6551B EQU $FF68 ; Set base address for future use
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
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42 ENDC
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be3446f758ca Updated dwread.asm and dwwrite.asm so that the 6551 routines could have specially defined
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43 IFNDEF SYDATA
be3446f758ca Updated dwread.asm and dwwrite.asm so that the 6551 routines could have specially defined
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44 SYDATA EQU SY6551B
be3446f758ca Updated dwread.asm and dwwrite.asm so that the 6551 routines could have specially defined
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parents: 3239
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45 ENDC
be3446f758ca Updated dwread.asm and dwwrite.asm so that the 6551 routines could have specially defined
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46 IFNDEF SYCONT
be3446f758ca Updated dwread.asm and dwwrite.asm so that the 6551 routines could have specially defined
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47 SYCONT EQU SY6551B+3
be3446f758ca Updated dwread.asm and dwwrite.asm so that the 6551 routines could have specially defined
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48 ENDC
be3446f758ca Updated dwread.asm and dwwrite.asm so that the 6551 routines could have specially defined
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49 IFNDEF SYCOMM
be3446f758ca Updated dwread.asm and dwwrite.asm so that the 6551 routines could have specially defined
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50 SYCOMM EQU SY6551B+2
be3446f758ca Updated dwread.asm and dwwrite.asm so that the 6551 routines could have specially defined
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51 ENDC
be3446f758ca Updated dwread.asm and dwwrite.asm so that the 6551 routines could have specially defined
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parents: 3239
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52 IFNDEF SYSTAT
be3446f758ca Updated dwread.asm and dwwrite.asm so that the 6551 routines could have specially defined
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parents: 3239
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53 SYSTAT EQU SY6551B+1
be3446f758ca Updated dwread.asm and dwwrite.asm so that the 6551 routines could have specially defined
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parents: 3239
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54 ENDC
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a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
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55 * NOTE: There is no timeout currently on here...
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
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parents: 3034
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56 DWRead clra ; clear Carry (no framing error)
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
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parents: 3034
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57 deca ; clear Z flag, A = timeout msb ($ff)
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
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58 tfr cc,b
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
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59 pshs u,x,dp,b,a ; preserve registers, push timeout msb
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
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parents: 3034
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60 leau ,x
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
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61 ldx #$0000
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
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62 IFEQ NOINTMASK
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
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63 orcc #IntMasks
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
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64 ENDC
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be3446f758ca Updated dwread.asm and dwwrite.asm so that the 6551 routines could have specially defined
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65 loop@ ldb SYSTAT
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a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
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66 andb #$08
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67 beq loop@
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68 ldb SYDATA
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69 stb ,u+
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
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70 abx
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
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71 leay ,-y
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
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72 bne loop@
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
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73
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
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parents: 3034
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74 tfr x,y
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
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75 ldb #0
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
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76 lda #3
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
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77 leas 1,s ; remove timeout msb from stack
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
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parents: 3034
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78 inca ; A = status to be returned in C and Z
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
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parents: 3034
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79 ora ,s ; place status information into the..
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
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parents: 3034
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80 sta ,s ; ..C and Z bits of the preserved CC
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
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parents: 3034
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81 leay ,x ; return checksum in Y
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
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parents: 3034
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82 puls cc,dp,x,u,pc ; restore registers and return
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
David Ladd <drencor-xeen@users.sourceforge.net>
parents: 3034
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83 ELSE
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84 IFNE JMCPBCK
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85 * NOTE: There is no timeout currently on here...
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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86 DWRead clra ; clear Carry (no framing error)
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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87 deca ; clear Z flag, A = timeout msb ($ff)
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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88 tfr cc,b
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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89 pshs u,x,dp,b,a ; preserve registers, push timeout msb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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90 leau ,x
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91 ldx #$0000
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92 orcc #IntMasks
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93 loop@ ldb $FF4C
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94 bitb #$02
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95 beq loop@
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96 ldb $FF44
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97 stb ,u+
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98 abx
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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99 leay ,-y
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100 bne loop@
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101
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102 tfr x,y
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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103 ldb #0
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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104 lda #3
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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105 leas 1,s ; remove timeout msb from stack
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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106 inca ; A = status to be returned in C and Z
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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107 ora ,s ; place status information into the..
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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parents: 2771
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108 sta ,s ; ..C and Z bits of the preserved CC
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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parents: 2771
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109 leay ,x ; return checksum in Y
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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parents: 2771
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110 puls cc,dp,x,u,pc ; restore registers and return
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
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111 ELSE
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112 IFNE BECKER
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113 IFNDEF BECKBASE
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parents: 3034
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114 BECKBASE EQU $FF41 ; Set base address for future use
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
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parents: 3034
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115 ENDC
3034
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
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116 * NOTE: There is no timeout currently on here...
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
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parents: 3031
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117 DWRead clra ; clear Carry (no framing error)
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
118 deca ; clear Z flag, A = timeout msb ($ff)
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
119 tfr cc,b
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
120 pshs u,x,dp,b,a ; preserve registers, push timeout msb
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
121 leau ,x
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
122 ldx #$0000
3030
41d88c40b023 Updated becker port routine with a timeout check.
David Ladd <drencor-xeen@users.sf.net>
parents: 2898
diff changeset
123 IFEQ NOINTMASK
3034
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
124 orcc #IntMasks
3030
41d88c40b023 Updated becker port routine with a timeout check.
David Ladd <drencor-xeen@users.sf.net>
parents: 2898
diff changeset
125 ENDC
3239
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
David Ladd <drencor-xeen@users.sourceforge.net>
parents: 3034
diff changeset
126 loop@ ldb BECKBASE
2772
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
127 bitb #$02
3034
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
128 beq loop@
3239
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
David Ladd <drencor-xeen@users.sourceforge.net>
parents: 3034
diff changeset
129 ldb BECKBASE+1
3034
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
130 stb ,u+
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
131 abx
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
132 leay ,-y
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
133 bne loop@
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
134 tfr x,y
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
135 ldb #0
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
136 lda #3
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
137 leas 1,s ; remove timeout msb from stack
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
138 inca ; A = status to be returned in C and Z
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
139 ora ,s ; place status information into the..
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
140 sta ,s ; ..C and Z bits of the preserved CC
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
141 leay ,x ; return checksum in Y
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
142 puls cc,dp,x,u,pc ; restore registers and return
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
143 ELSE
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
144 IFNE BECKERTO
3239
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
David Ladd <drencor-xeen@users.sourceforge.net>
parents: 3034
diff changeset
145 IFNDEF BECKBASE
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
David Ladd <drencor-xeen@users.sourceforge.net>
parents: 3034
diff changeset
146 BECKBASE EQU $FF41 ; Set base address for future use
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
David Ladd <drencor-xeen@users.sourceforge.net>
parents: 3034
diff changeset
147 ENDC
3034
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
148 * NOTE: There is now timeout ...
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
149 DWRead clra ; clear Carry, Set Z
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
150 pshs cc,x,u ; save regs
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
151 leau ,x ; U is data buffer
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
152 ldx #$0000 ; X is reset check sum
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
153 IFEQ NOINTMASK
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
154 orcc #IntMasks ; turn off interrupts
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
155 ENDC
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
156 ini@ pshs x ; save X
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
157 ldx #0x8000 ; X = timeout
3239
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
David Ladd <drencor-xeen@users.sourceforge.net>
parents: 3034
diff changeset
158 loop@ ldb BECKBASE ; test for data ready flag
3034
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
159 bitb #$02
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
160 bne rdy@ ; byte is ready
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
161 leax -1,x ; bump timout
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
162 bne loop@ ; not timed out, try again
3030
41d88c40b023 Updated becker port routine with a timeout check.
David Ladd <drencor-xeen@users.sf.net>
parents: 2898
diff changeset
163 ;; timed out!
3034
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
164 puls x ; remove timeout off stack
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
165 puls cc ; pull CC
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
166 comb ; reset Z (timeout error)
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
167 puls x,u,pc ; restore registers and return
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
168 ;; a byte is ready
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
169 rdy@ puls x ; restore X
3239
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
David Ladd <drencor-xeen@users.sourceforge.net>
parents: 3034
diff changeset
170 ldb BECKBASE+1 ; get byte from port
3030
41d88c40b023 Updated becker port routine with a timeout check.
David Ladd <drencor-xeen@users.sf.net>
parents: 2898
diff changeset
171 stb ,u+ ; store in data buffer
41d88c40b023 Updated becker port routine with a timeout check.
David Ladd <drencor-xeen@users.sf.net>
parents: 2898
diff changeset
172 abx ; add received byte to checksum
41d88c40b023 Updated becker port routine with a timeout check.
David Ladd <drencor-xeen@users.sf.net>
parents: 2898
diff changeset
173 leay ,-y ; decrement byte counter
41d88c40b023 Updated becker port routine with a timeout check.
David Ladd <drencor-xeen@users.sf.net>
parents: 2898
diff changeset
174 bne ini@ ; go get another byte if not done
3034
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
175 ;; done reading bytes return
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
176 tfr x,y ; put checksum in y
3030
41d88c40b023 Updated becker port routine with a timeout check.
David Ladd <drencor-xeen@users.sf.net>
parents: 2898
diff changeset
177 puls cc,x,u,pc ; restore registers and return
3034
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
178
f818de1b815a Moved becker routine with timeout to a new driver called BECKERTO and restored original BECKER routine from backup.
David Ladd <drencor-xeen@users.sf.net>
parents: 3031
diff changeset
179 ENDC
2772
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
180 ENDC
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
181 ENDC
3239
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
David Ladd <drencor-xeen@users.sourceforge.net>
parents: 3034
diff changeset
182 ENDC
2772
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
183
3239
a47ee8f14eb8 Added new routine to dwread.asm and dwwrite.asm for using the SY6551 chips.
David Ladd <drencor-xeen@users.sourceforge.net>
parents: 3034
diff changeset
184 IFEQ BECKER+JMCPBCK+ARDUINO+BECKERTO+SY6551N
2772
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
185 IFNE BAUD38400
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
186 *******************************************************
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
187 * 38400 bps using 6809 code and timimg
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
188 *******************************************************
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
189
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
190 DWRead clra ; clear Carry (no framing error)
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
191 deca ; clear Z flag, A = timeout msb ($ff)
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
192 tfr cc,b
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
193 pshs u,x,dp,b,a ; preserve registers, push timeout msb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
194 orcc #$50 ; mask interrupts
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
195 tfr a,dp ; set direct page to $FFxx
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
196 setdp $ff
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
197 leau ,x ; U = storage ptr
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
198 ldx #0 ; initialize checksum
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
199 adda #2 ; A = $01 (serial in mask), set Carry
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
200
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
201 * Wait for a start bit or timeout
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
202 rx0010 bcc rxExit ; exit if timeout expired
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
203 ldb #$ff ; init timeout lsb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
204 rx0020 bita <BBIN ; check for start bit
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
205 beq rxByte ; branch if start bit detected
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
206 subb #1 ; decrement timeout lsb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
207 bita <BBIN
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
208 beq rxByte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
209 bcc rx0020 ; loop until timeout lsb rolls under
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
210 bita <BBIN
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
211 beq rxByte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
212 addb ,s ; B = timeout msb - 1
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
213 bita <BBIN
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
214 beq rxByte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
215 stb ,s ; store decremented timeout msb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
216 bita <BBIN
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
217 bne rx0010 ; loop if still no start bit
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
218
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
219 * Read a byte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
220 rxByte leay ,-y ; decrement request count
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
221 ldd #$ff80 ; A = timeout msb, B = shift counter
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
222 sta ,s ; reset timeout msb for next byte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
223 rx0030 exg a,a
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
224 nop
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
225 lda <BBIN ; read data bit
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
226 lsra ; shift into carry
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
227 rorb ; rotate into byte accumulator
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
228 lda #$01 ; prep stop bit mask
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
229 bcc rx0030 ; loop until all 8 bits read
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
230
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
231 stb ,u+ ; store received byte to memory
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
232 abx ; update checksum
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
233 ldb #$ff ; set timeout lsb for next byte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
234 anda <BBIN ; read stop bit
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
235 beq rxExit ; exit if framing error
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
236 leay ,y ; test request count
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
237 bne rx0020 ; loop if another byte wanted
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
238 lda #$03 ; setup to return SUCCESS
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
239
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
240 * Clean up, set status and return
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
241 rxExit leas 1,s ; remove timeout msb from stack
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
242 inca ; A = status to be returned in C and Z
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
243 ora ,s ; place status information into the..
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
244 sta ,s ; ..C and Z bits of the preserved CC
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
245 leay ,x ; return checksum in Y
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
246 puls cc,dp,x,u,pc ; restore registers and return
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
247 setdp $00
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
248
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
249
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
250 ELSE
2770
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
251 IFEQ H6309
2772
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
252 *******************************************************
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
253 * 57600 (115200) bps using 6809 code and timimg
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
254 *******************************************************
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
255
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
256 DWRead clra ; clear Carry (no framing error)
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
257 deca ; clear Z flag, A = timeout msb ($ff)
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
258 tfr cc,b
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
259 pshs u,x,dp,b,a ; preserve registers, push timeout msb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
260 orcc #$50 ; mask interrupts
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
261 tfr a,dp ; set direct page to $FFxx
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
262 setdp $ff
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
263 leau ,x ; U = storage ptr
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
264 ldx #0 ; initialize checksum
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
265 lda #$01 ; A = serial in mask
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
266 bra rx0030 ; go wait for start bit
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
267
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
268 * Read a byte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
269 rxByte leau 1,u ; bump storage ptr
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
270 leay ,-y ; decrement request count
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
271 lda <BBIN ; read bit 0
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
272 lsra ; move bit 0 into Carry
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
273 ldd #$ff20 ; A = timeout msb, B = shift counter
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
274 sta ,s ; reset timeout msb for next byte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
275 rorb ; rotate bit 0 into byte accumulator
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
276 rx0010 lda <BBIN ; read bit (d1, d3, d5)
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
277 lsra
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
278 rorb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
279 bita 1,s ; 5 cycle delay
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
280 bcs rx0020 ; exit loop after reading bit 5
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
281 lda <BBIN ; read bit (d2, d4)
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
282 lsra
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
283 rorb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
284 leau ,u
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
285 bra rx0010
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
286
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
287 rx0020 lda <BBIN ; read bit 6
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
288 lsra
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
289 rorb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
290 leay ,y ; test request count
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
291 beq rx0050 ; branch if final byte of request
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
292 lda <BBIN ; read bit 7
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
293 lsra
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
294 rorb ; byte is now complete
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
295 stb -1,u ; store received byte to memory
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
296 abx ; update checksum
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
297 lda <BBIN ; read stop bit
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
298 anda #$01 ; mask out other bits
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
299 beq rxExit ; exit if framing error
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
300
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
301 * Wait for a start bit or timeout
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
302 rx0030 bita <BBIN ; check for start bit
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
303 beq rxByte ; branch if start bit detected
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
304 bita <BBIN ; again
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
305 beq rxByte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
306 ldb #$ff ; init timeout lsb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
307 rx0040 bita <BBIN
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
308 beq rxByte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
309 subb #1 ; decrement timeout lsb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
310 bita <BBIN
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
311 beq rxByte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
312 bcc rx0040 ; loop until timeout lsb rolls under
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
313 bita <BBIN
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
314 beq rxByte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
315 addb ,s ; B = timeout msb - 1
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
316 bita <BBIN
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
317 beq rxByte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
318 stb ,s ; store decremented timeout msb
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
319 bita <BBIN
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
320 beq rxByte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
321 bcs rx0030 ; loop if timeout hasn't expired
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
322 bra rxExit ; exit due to timeout
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
323
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
324 rx0050 lda <BBIN ; read bit 7 of final byte
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
325 lsra
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
326 rorb ; byte is now complete
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
327 stb -1,u ; store received byte to memory
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
328 abx ; calculate final checksum
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
329 lda <BBIN ; read stop bit
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
330 anda #$01 ; mask out other bits
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
331 ora #$02 ; return SUCCESS if no framing error
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
332
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
333 * Clean up, set status and return
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
334 rxExit leas 1,s ; remove timeout msb from stack
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
335 inca ; A = status to be returned in C and Z
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
336 ora ,s ; place status information into the..
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
337 sta ,s ; ..C and Z bits of the preserved CC
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
338 leay ,x ; return checksum in Y
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
339 puls cc,dp,x,u,pc ; restore registers and return
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
340 setdp $00
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
341
2770
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
342
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
343 ELSE
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
344 *******************************************************
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
345 * 57600 (115200) bps using 6309 native mode
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
346 *******************************************************
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
347
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
348 DWRead clrb ; clear Carry (no framing error)
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
349 decb ; clear Z flag, B = $FF
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
350 pshs u,x,dp,cc ; preserve registers
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
351 orcc #$50 ; mask interrupts
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
352 * ldmd #1 ; requires 6309 native mode
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
353 tfr b,dp ; set direct page to $FFxx
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
354 setdp $ff
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
355 leay -1,y ; adjust request count
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
356 leau ,x ; U = storage ptr
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
357 tfr 0,x ; initialize checksum
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
358 lda #$01 ; A = serial in mask
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
359 bra rx0030 ; go wait for start bit
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
360
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
361 * Read a byte
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
362 rxByte sexw ; 4 cycle delay
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
363 ldw #$006a ; shift counter and timing flags
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
364 clra ; clear carry so next will branch
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
365 rx0010 bcc rx0020 ; branch if even bit number (15 cycles)
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
366 nop ; extra (16th) cycle
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
367 rx0020 lda <BBIN ; read bit
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
368 lsra ; move bit into carry
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
369 rorb ; rotate bit into byte accumulator
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
370 lda #0 ; prep A for 8th data bit
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
371 lsrw ; bump shift count, timing bit to carry
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
372 bne rx0010 ; loop until 7th data bit has been read
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
373 incw ; W = 1 for subtraction from Y
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
374 inca ; A = 1 for reading bit 7
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
375 anda <BBIN ; read bit 7
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
376 lsra ; move bit 7 into carry, A = 0
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
377 rorb ; byte is now complete
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
378 stb ,u+ ; store received byte to memory
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
379 abx ; update checksum
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
380 subr w,y ; decrement request count
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
381 inca ; A = 1 for reading stop bit
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
382 anda <BBIN ; read stop bit
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
383 bls rxExit ; exit if completed or framing error
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
384
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
385 * Wait for a start bit or timeout
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
386 rx0030 clrw ; initialize timeout counter
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
387 rx0040 bita <BBIN ; check for start bit
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
388 beq rxByte ; branch if start bit detected
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
389 addw #1 ; bump timeout counter
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
390 bita <BBIN
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
391 beq rxByte
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
392 bcc rx0040 ; loop until timeout rolls over
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
393 lda #$03 ; setup to return TIMEOUT status
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
394
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
395 * Clean up, set status and return
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
396 rxExit beq rx0050 ; branch if framing error
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
397 eora #$02 ; toggle SUCCESS flag
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
398 rx0050 inca ; A = status to be returned in C and Z
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
399 ora ,s ; place status information into the..
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
400 sta ,s ; ..C and Z bits of the preserved CC
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
401 leay ,x ; return checksum in Y
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
402 puls cc,dp,x,u,pc ; restore registers and return
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
403 setdp $00
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
404
2772
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
405 ENDC
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
406 ENDC
0a3f4d8ea6d5 Found ENDC in wrong location in dwread.asm and dwwrite.asm. Corrected.
drencor-xeen
parents: 2771
diff changeset
407 ENDC
2770
bfe3de781ddf Added Arduino dwread/dwwrite changes
Boisy Pitre <boisy.pitre@nuance.com>
parents: 2725
diff changeset
408 ENDC